RV_TIMER Simulation Results

Wednesday September 24 2025 16:10:09 UTC

GitHub Revision: f250b50

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.930s	115.412us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.780s	20.131us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.760s	27.081us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.090s	499.397us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.800s	65.859us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.840s	45.612us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.760s	27.081us	1	1	100.00
		rv_timer_csr_aliasing	0.800s	65.859us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.020s	162.646us	0	1	0.00
V2	disabled	rv_timer_disabled	2.880s	2.118ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	4.354m	1.443s	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	4.354m	1.443s	1	1	100.00
V2	stress	rv_timer_stress_all	1.880s	2.054ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.580s	39.471us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.540s	52.409us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.400s	83.920us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.400s	83.920us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.780s	20.131us	1	1	100.00
		rv_timer_csr_rw	0.760s	27.081us	1	1	100.00
		rv_timer_csr_aliasing	0.800s	65.859us	1	1	100.00
		rv_timer_same_csr_outstanding	0.880s	42.791us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.780s	20.131us	1	1	100.00
		rv_timer_csr_rw	0.760s	27.081us	1	1	100.00
		rv_timer_csr_aliasing	0.800s	65.859us	1	1	100.00
		rv_timer_same_csr_outstanding	0.880s	42.791us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.710s	72.528us	1	1	100.00
		rv_timer_tl_intg_err	1.660s	143.898us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.660s	143.898us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.720s	23.278us	1	1	100.00
V3	max_value	rv_timer_max	0.870s	441.822us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	10.340s	3.674ms	1	1	100.00
V3		TOTAL			2	3	66.67
		TOTAL			17	19	89.47

Failure Buckets

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.46253186473296335704461612114331384223122259119815612913080630654881211361290
      Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @ 441822210 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 441822210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 1 failures:

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.107634450007206403191593748273746845389498449801542660521304384023140671648262
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 162646170 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xf64b9104) == 0x1
        UVM_INFO @ 162646170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---