SPI_DEVICE/1R1W Simulation Results

Wednesday September 24 2025 16:10:09 UTC

GitHub Revision: f250b50

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	29.740s	4.260ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.110s	40.037us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.770s	225.644us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	8.350s	750.509us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	5.320s	442.391us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.910s	57.836us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.770s	225.644us	1	1	100.00
		spi_device_csr_aliasing	5.320s	442.391us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.820s	11.756us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.670s	96.379us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.160s	52.480us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.000s	1.897us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.840s	7.418us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	0.830s	35.839us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	0.830s	35.839us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	0.830s	25.267us	1	1	100.00
		spi_device_tpm_sts_read	0.920s	64.090us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	31.760s	8.232ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	11.500s	21.937ms	1	1	100.00
		spi_device_flash_all	51.400s	6.121ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.540s	2.833ms	1	1	100.00
		spi_device_flash_all	51.400s	6.121ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.540s	2.833ms	1	1	100.00
		spi_device_flash_all	51.400s	6.121ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	51.400s	6.121ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	10.490s	5.285ms	1	1	100.00
		spi_device_flash_all	51.400s	6.121ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	10.490s	5.285ms	1	1	100.00
		spi_device_flash_all	51.400s	6.121ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	10.490s	5.285ms	1	1	100.00
		spi_device_flash_all	51.400s	6.121ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	10.490s	5.285ms	1	1	100.00
		spi_device_flash_all	51.400s	6.121ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	10.490s	5.285ms	1	1	100.00
		spi_device_flash_all	51.400s	6.121ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	11.020s	5.035ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	4.060s	368.754us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	4.060s	368.754us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	4.060s	368.754us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	6.800s	479.518us	1	1	100.00
		spi_device_read_buffer_direct	6.420s	1.513ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	4.060s	368.754us	1	1	100.00
		spi_device_flash_all	51.400s	6.121ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	51.400s	6.121ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	51.400s	6.121ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	5.640s	4.041ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	5.640s	4.041ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	29.740s	4.260ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	25.970s	1.629ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.261m	118.527ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.840s	17.110us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.770s	13.128us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.120s	165.698us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.120s	165.698us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.110s	40.037us	1	1	100.00
		spi_device_csr_rw	1.770s	225.644us	1	1	100.00
		spi_device_csr_aliasing	5.320s	442.391us	1	1	100.00
		spi_device_same_csr_outstanding	2.480s	485.354us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.110s	40.037us	1	1	100.00
		spi_device_csr_rw	1.770s	225.644us	1	1	100.00
		spi_device_csr_aliasing	5.320s	442.391us	1	1	100.00
		spi_device_same_csr_outstanding	2.480s	485.354us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.450s	93.767us	1	1	100.00
		spi_device_tl_intg_err	10.700s	711.286us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	10.700s	711.286us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.393m	60.194ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.65010975960826171310957916556602830983247012439019976741803946731388787625649
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1536549 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[89])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1536549 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1536549 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[985])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.33451183572041107912687536904289181347810243320722615489546818258236883330951
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   5024630 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf8dfad [111110001101111110101101] vs 0x0 [0])
        UVM_ERROR @   5036630 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5653d3 [10101100101001111010011] vs 0x0 [0])
        UVM_ERROR @   5055630 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xdedc23 [110111101101110000100011] vs 0x0 [0])
        UVM_ERROR @   5068630 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x10c447 [100001100010001000111] vs 0x0 [0])
        UVM_ERROR @   5122630 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4f36a8 [10011110011011010101000] vs 0x0 [0])