SPI_HOST Simulation Results

Wednesday September 24 2025 16:10:09 UTC

GitHub Revision: f250b50

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	49.000s	13.933ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	1.000s	42.329us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	45.514us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	3.000s	778.359us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	1.000s	21.450us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	30.290us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	45.514us	1	1	100.00
		spi_host_csr_aliasing	1.000s	21.450us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	24.956us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	19.822us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	9.000s	80.729us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	9.000s	53.434us	1	1	100.00
		spi_host_error_cmd	9.000s	50.902us	1	1	100.00
		spi_host_event	14.000s	865.544us	1	1	100.00
V2	clock_rate	spi_host_speed	11.000s	259.395us	1	1	100.00
V2	speed	spi_host_speed	11.000s	259.395us	1	1	100.00
V2	chip_select_timing	spi_host_speed	11.000s	259.395us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	33.000s	2.707ms	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	6.000s	91.594us	1	1	100.00
V2	cpol_cpha	spi_host_speed	11.000s	259.395us	1	1	100.00
V2	full_cycle	spi_host_speed	11.000s	259.395us	1	1	100.00
V2	duplex	spi_host_smoke	49.000s	13.933ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	49.000s	13.933ms	1	1	100.00
V2	stress_all	spi_host_stress_all	1.833m	24.612ms	1	1	100.00
V2	spien	spi_host_spien	6.000s	832.133us	1	1	100.00
V2	stall	spi_host_status_stall	1.200m	37.896ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	17.000s	14.881ms	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	9.000s	53.434us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	50.385us	1	1	100.00
V2	intr_test	spi_host_intr_test	2.000s	51.279us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	3.000s	204.376us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	3.000s	204.376us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	1.000s	42.329us	1	1	100.00
		spi_host_csr_rw	2.000s	45.514us	1	1	100.00
		spi_host_csr_aliasing	1.000s	21.450us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	38.485us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	1.000s	42.329us	1	1	100.00
		spi_host_csr_rw	2.000s	45.514us	1	1	100.00
		spi_host_csr_aliasing	1.000s	21.450us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	38.485us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	121.391us	1	1	100.00
		spi_host_sec_cm	4.000s	386.409us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	121.391us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	41.000s	1.876ms	1	1	100.00
		TOTAL			26	26	100.00