SRAM_CTRL/MAIN Simulation Results

Wednesday September 24 2025 16:10:09 UTC

GitHub Revision: f250b50

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	16.920s	1.120ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.810s	33.611us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.930s	17.211us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.580s	180.905us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.000s	24.480us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.710s	358.721us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.930s	17.211us	1	1	100.00
		sram_ctrl_csr_aliasing	1.000s	24.480us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.603m	27.632ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	53.180s	4.028ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	9.710m	16.314ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.662m	27.988ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	15.569m	300.277ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	5.123m	6.837ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	18.130s	21.217ms	1	1	100.00
V2	executable	sram_ctrl_executable	4.638m	22.302ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	14.370s	624.861us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.105m	14.168ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	4.030s	701.611us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	5.710s	842.638us	1	1	100.00
		sram_ctrl_throughput_w_readback	1.002m	1.885ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	3.524m	12.601ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.790s	344.784us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	58.734m	597.961ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.940s	57.252us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.350s	159.461us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.350s	159.461us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.810s	33.611us	1	1	100.00
		sram_ctrl_csr_rw	0.930s	17.211us	1	1	100.00
		sram_ctrl_csr_aliasing	1.000s	24.480us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.960s	25.768us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.810s	33.611us	1	1	100.00
		sram_ctrl_csr_rw	0.930s	17.211us	1	1	100.00
		sram_ctrl_csr_aliasing	1.000s	24.480us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.960s	25.768us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	15.290s	4.255ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.880s	10.295us	0	1	0.00
		sram_ctrl_tl_intg_err	1.340s	435.147us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.880s	10.295us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.340s	435.147us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	3.524m	12.601ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	3.524m	12.601ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.930s	17.211us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.638m	22.302ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.638m	22.302ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.638m	22.302ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	18.130s	21.217ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	7.330s	1.344ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	15.290s	4.255ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.220s	707.566us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	16.920s	1.120ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	16.920s	1.120ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.638m	22.302ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.880s	10.295us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	18.130s	21.217ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.880s	10.295us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.880s	10.295us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	16.920s	1.120ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.880s	10.295us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	24.240s	3.498ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.37259447298799479103449111830786269506186026717953515692634149808755502566292
      Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  10294568 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  10294568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---