SRAM_CTRL/RET Simulation Results

Wednesday September 24 2025 16:10:09 UTC

GitHub Revision: f250b50

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	3.330s	88.093us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.940s	13.225us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.830s	30.302us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.540s	52.422us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.750s	206.253us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.690s	140.027us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.830s	30.302us	1	1	100.00
		sram_ctrl_csr_aliasing	0.750s	206.253us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.720s	2.092ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.000s	401.309us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	10.349m	13.035ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.488m	3.626ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	34.230s	9.794ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.750m	2.259ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.940s	779.806us	1	1	100.00
V2	executable	sram_ctrl_executable	1.688m	5.725ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	4.760s	169.303us	1	1	100.00
		sram_ctrl_partial_access_b2b	2.543m	7.241ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	48.910s	151.783us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	7.860s	140.028us	1	1	100.00
		sram_ctrl_throughput_w_readback	3.860s	330.376us	1	1	100.00
V2	regwen	sram_ctrl_regwen	8.481m	2.778ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.970s	29.345us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	43.568m	68.767ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.800s	13.270us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.560s	130.895us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.560s	130.895us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.940s	13.225us	1	1	100.00
		sram_ctrl_csr_rw	0.830s	30.302us	1	1	100.00
		sram_ctrl_csr_aliasing	0.750s	206.253us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.790s	13.349us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.940s	13.225us	1	1	100.00
		sram_ctrl_csr_rw	0.830s	30.302us	1	1	100.00
		sram_ctrl_csr_aliasing	0.750s	206.253us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.790s	13.349us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.620s	1.228ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.860s	2.476us	0	1	0.00
		sram_ctrl_tl_intg_err	1.590s	141.018us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.860s	2.476us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.590s	141.018us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	8.481m	2.778ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	8.481m	2.778ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.830s	30.302us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	1.688m	5.725ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	1.688m	5.725ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	1.688m	5.725ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.940s	779.806us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.230s	146.089us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.620s	1.228ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.970s	111.557us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	3.330s	88.093us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	3.330s	88.093us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	1.688m	5.725ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.860s	2.476us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.940s	779.806us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.860s	2.476us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.860s	2.476us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	3.330s	88.093us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.860s	2.476us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	47.810s	1.080ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(depth_o <= *'(Depth))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.70774019192027240803721457742699027540800363743619788964510360281559368194102
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   2475568 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   2475568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---