UART Simulation Results

Wednesday September 24 2025 16:10:09 UTC

GitHub Revision: f250b50

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.280s	490.541us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.750s	19.025us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.750s	54.770us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.430s	1.203ms	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.740s	22.618us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.790s	159.226us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.750s	54.770us	1	1	100.00
		uart_csr_aliasing	0.740s	22.618us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	1.618m	81.912ms	1	1	100.00
V2	parity	uart_smoke	1.280s	490.541us	1	1	100.00
		uart_tx_rx	1.618m	81.912ms	1	1	100.00
V2	parity_error	uart_intr	7.890s	12.321ms	1	1	100.00
		uart_rx_parity_err	59.520s	373.290ms	1	1	100.00
V2	watermark	uart_tx_rx	1.618m	81.912ms	1	1	100.00
		uart_intr	7.890s	12.321ms	1	1	100.00
V2	fifo_full	uart_fifo_full	15.550s	52.670ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	21.800s	60.142ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	2.226m	121.536ms	1	1	100.00
V2	rx_frame_err	uart_intr	7.890s	12.321ms	1	1	100.00
V2	rx_break_err	uart_intr	7.890s	12.321ms	1	1	100.00
V2	rx_timeout	uart_intr	7.890s	12.321ms	1	1	100.00
V2	perf	uart_perf	4.224m	30.455ms	1	1	100.00
V2	sys_loopback	uart_loopback	15.500s	11.350ms	1	1	100.00
V2	line_loopback	uart_loopback	15.500s	11.350ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	2.960s	3.982ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	30.830s	36.501ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.700s	8.425ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	26.120s	4.854ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	5.030m	91.033ms	1	1	100.00
V2	stress_all	uart_stress_all	1.135m	185.728ms	0	1	0.00
V2	alert_test	uart_alert_test	0.810s	13.781us	1	1	100.00
V2	intr_test	uart_intr_test	0.580s	83.351us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.020s	521.857us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.020s	521.857us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.750s	19.025us	1	1	100.00
		uart_csr_rw	0.750s	54.770us	1	1	100.00
		uart_csr_aliasing	0.740s	22.618us	1	1	100.00
		uart_same_csr_outstanding	0.780s	58.992us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.750s	19.025us	1	1	100.00
		uart_csr_rw	0.750s	54.770us	1	1	100.00
		uart_csr_aliasing	0.740s	22.618us	1	1	100.00
		uart_same_csr_outstanding	0.780s	58.992us	1	1	100.00
V2		TOTAL			16	18	88.89
V2S	tl_intg_err	uart_sec_cm	1.070s	152.354us	1	1	100.00
		uart_tl_intg_err	1.370s	355.080us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.370s	355.080us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	47.510s	15.777ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			24	27	88.89

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 2 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 0.uart_stress_all_with_rand_reset.79265164530554618532097286432270903680569095176942284798131148833661540329802
      Line 128, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6251347208 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 6251347208 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 6251347208 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 6299770866 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 6300463182 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

  • Test uart_stress_all has 1 failures.

    • 0.uart_stress_all.95391653288634079113927942411123466453406859677069958673680422160295637529349
      Line 82, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log

        UVM_ERROR @ 118429806059 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 118429806059 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 118429806059 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 118582098944 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 9
        UVM_ERROR @ 118582140611 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
      

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.113975320081217991094149078141097206149540915687945258341179173724094566497293
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 395123707 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
        UVM_ERROR @ 395165374 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 395498710 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 395540377 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 395623711 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 239 [0xef]) reg name: uart_reg_block.rdata