CHIP Simulation Results

Wednesday September 24 2025 16:10:09 UTC

GitHub Revision: `f250b50`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.775m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.775m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	30.448s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	36.748s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	55.804s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.844m	6.285ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.844m	6.285ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.844m	6.285ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	30.430s	10.300us	0	1	0.00
		chip_sw_example_manufacturer	2.412m		0	1	0.00
		chip_sw_example_concurrency	5.250m	4.431ms	1	1	100.00
		chip_sw_uart_smoketest_signed	11.539s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.770s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	9.630s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	9.630s		0	1	0.00
V1	xbar_smoke	xbar_smoke	8.300s	11.752us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.158m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	10.870m	7.781ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.225m	4.393ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	16.438s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	14.949s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	23.008s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	12.426s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.040s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.040s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.491m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.843m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.348m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.348m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.855m	3.304ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.964m	3.432ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	8.270m	15.519ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.517s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	14.048s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	12.568m	17.536ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.278m	6.237ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	24.237m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	24.237m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	16.163s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.634m	4.191ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.634m	4.191ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	8.466m	18.019ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.162m	5.123ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	7.209m	5.245ms	1	1	100.00
		chip_sw_aes_idle	4.455m	5.568ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.286m	3.438ms	1	1	100.00
		chip_sw_kmac_idle	4.097m	3.501ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	15.344m	12.018ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	12.425m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	14.474m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	12.564m	12.027ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	12.237s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.510s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.062s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.086s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.277s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.980s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.922s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	12.237s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.510s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.062s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.086s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.277s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.980s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.922s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	14.354s		0	1	0.00
		chip_sw_aes_enc_jitter_en	40.740s	10.320us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	36.400s	10.200us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	36.160s	10.160us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	36.380s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.219s		0	1	0.00
		chip_sw_clkmgr_jitter	4.605m	5.401ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.114m	5.734ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	13.871s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	37.350s	10.360us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	39.000s	10.340us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	46.140s	10.340us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	56.120s	10.160us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	36.310s	10.360us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	11.720s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.899s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	13.030s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.932s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	22.081m	15.954ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.320m	12.464ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.634m	4.191ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	13.713s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.320m	12.464ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	14.036s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	14.761s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	14.510s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	20.623s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	12.330s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	22.081m	15.954ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	8.270m	15.519ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	24.497m	20.027ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.907m	7.307ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	8.692m	7.296ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.608m	3.804ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	22.081m	15.954ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	11.348s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	12.505s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	22.081m	15.954ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	14.179s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	8.692m	7.296ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	12.148s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	13.274s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	12.113s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	13.699s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	12.980s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	13.927s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	12.505s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	12.983s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	19.597s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	12.983s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	12.983s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	12.983s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	8.546m	8.327ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	13.219s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	13.541s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	17.957s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	14.116s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.983s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	9.340m	10.101ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	11.344m	14.030ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	13.018s		0	1	0.00
		chip_prim_tl_access	9.503m	13.879ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	12.237s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.510s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.062s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.086s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.277s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.980s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.922s		0	1	0.00
		chip_rv_dm_lc_disabled	12.568m	17.536ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.913m	3.429ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	40.740s	10.320us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.712m	4.229ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.455m	5.568ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.837m	3.883ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	36.400s	10.200us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.286m	3.438ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.459m	5.893ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.961m	5.298ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	36.380s	10.200us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	9.340m	10.101ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	12.983s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	33.330s	10.180us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	7.061m	5.898ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.097m	3.501ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.173s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.173s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.139s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.845m	3.779ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.003s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	9.340m	10.101ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	36.160s	10.160us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	14.920s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	14.354s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	7.209m	5.245ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	7.209m	5.245ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	7.209m	5.245ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.423m	5.253ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	11.344m	14.030ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	11.344m	14.030ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	10.626m	9.606ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.219s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	13.018s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	22.081m	15.954ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.348m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	12.983s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.423m	5.253ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	9.340m	10.101ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	10.626m	9.606ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.778m	3.305ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.423m	5.253ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	9.340m	10.101ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	10.626m	9.606ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.778m	3.305ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	12.983s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	12.097s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	19.597s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	13.219s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	13.541s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	17.957s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	14.116s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.983s		0	1	0.00
		chip_prim_tl_access	9.503m	13.879ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	9.503m	13.879ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	11.775s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	14.041s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.899s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	14.354s		0	1	0.00
		chip_sw_aes_enc_jitter_en	40.740s	10.320us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	36.400s	10.200us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	36.160s	10.160us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	36.380s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.219s		0	1	0.00
		chip_sw_clkmgr_jitter	4.605m	5.401ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	8.832m	9.452ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	8.832m	9.452ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	5.716m	5.175ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.721m	3.481ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	5.104m	4.652ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.121m	6.363ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	6.504m	4.630ms	0	1	0.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.845m	3.700ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.778m	3.305ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	24.497m	20.027ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	24.497m	20.027ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	4.438m	5.061ms	1	1	100.00
		chip_sw_aon_timer_smoketest	4.009m	5.223ms	1	1	100.00
		chip_sw_clkmgr_smoketest	4.324m	4.885ms	1	1	100.00
		chip_sw_csrng_smoketest	3.687m	4.799ms	1	1	100.00
		chip_sw_gpio_smoketest	3.974m	4.302ms	1	1	100.00
		chip_sw_hmac_smoketest	5.200m	5.089ms	1	1	100.00
		chip_sw_kmac_smoketest	4.364m	6.120ms	1	1	100.00
		chip_sw_otbn_smoketest	5.302m	5.619ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.745m	5.701ms	1	1	100.00
		chip_sw_rv_plic_smoketest	4.505m	5.851ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.622m	4.539ms	1	1	100.00
		chip_sw_rstmgr_smoketest	4.602m	5.631ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.973m	3.729ms	1	1	100.00
		chip_sw_uart_smoketest	3.260m	3.567ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	12.689s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	11.539s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.158m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	11.931s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.327m	3.882ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.412m	5.673ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.518m	4.746ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.015m	6.390ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	11.882s		0	1	0.00
		chip_rv_dm_lc_disabled	12.568m	17.536ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	13.766s		0	1	0.00
		chip_sw_lc_walkthrough_prod	15.245s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	12.374s		0	1	0.00
		chip_sw_lc_walkthrough_rma	14.299s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	11.882s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	18.160s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	15.904s		0	1	0.00
		rom_volatile_raw_unlock	11.434s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.539s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	39.871s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	48.554s		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.908m	3.372ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.908m	3.372ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	9.630s		0	1	0.00
		chip_same_csr_outstanding	8.560s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	9.630s		0	1	0.00
		chip_same_csr_outstanding	8.560s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	3.150m	526.722us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.310s	12.100us	1	1	100.00
		xbar_smoke_large_delays	4.507m	2.295ms	1	1	100.00
		xbar_smoke_slow_rsp	5.440m	2.001ms	1	1	100.00
		xbar_random_zero_delays	40.310s	37.670us	1	1	100.00
		xbar_random_large_delays	22.149m	11.207ms	1	1	100.00
		xbar_random_slow_rsp	18.606m	6.483ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	30.730s	18.769us	1	1	100.00
		xbar_error_and_unmapped_addr	11.650s	22.631us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	2.330m	391.295us	1	1	100.00
		xbar_error_and_unmapped_addr	11.650s	22.631us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.293m	129.880us	1	1	100.00
		xbar_access_same_device_slow_rsp	55.380m	21.823ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	13.570s	15.548us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	4.304m	205.415us	1	1	100.00
		xbar_stress_all_with_error	21.972m	3.523ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	24.291m	2.754ms	1	1	100.00
		xbar_stress_all_with_reset_error	12.018m	486.893us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	14.453s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	13.131s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	13.385s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.844s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	13.190s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	15.059s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	12.918s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	13.020s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	13.348s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	13.655s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	13.076s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	13.637s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	14.045s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	53.941s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	49.265s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	44.303s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	45.395s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	47.594s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	47.574s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	44.527s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	37.317s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	38.259s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	34.886s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	31.726s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	39.772s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	34.491s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	36.356s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	33.428s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	17.621s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	14.593s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	23.016s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	13.440s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	14.559s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	17.625s		0	1	0.00
		rom_e2e_asm_init_dev	12.116s		0	1	0.00
		rom_e2e_asm_init_prod	12.882s		0	1	0.00
		rom_e2e_asm_init_prod_end	13.297s		0	1	0.00
		rom_e2e_asm_init_rma	12.449s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	12.557s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	12.176s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	12.928s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	12.044s		0	1	0.00
V2		TOTAL			64	205	31.22
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.815m	4.602ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.876m	5.260ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	12.271s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.941s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.427s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	13.951s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	22.081m	15.954ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	15.390s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	19.554m	15.909ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	11.632s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	11.956s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	12.271s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.941s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.427s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	12.647s		0	1	0.00
		rom_e2e_jtag_inject_dev	12.074s		0	1	0.00
		rom_e2e_jtag_inject_rma	12.618s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.691s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	22.568m	15.902ms	1	1	100.00
		chip_sw_entropy_src_kat_test	4.357m	4.094ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	3.718m	3.904ms	1	1	100.00
		chip_plic_all_irqs_0	9.473m	5.205ms	1	1	100.00
		chip_plic_all_irqs_10	12.215m	6.392ms	1	1	100.00
		chip_sw_dma_inline_hashing	5.589m	6.218ms	1	1	100.00
		chip_sw_dma_abort	4.136m	5.006ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	12.296s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	12.168s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.643s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.622s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.724s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	12.040s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.516s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.652s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	12.266s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.764s		0	1	0.00
		chip_sw_entropy_src_smoketest	5.340m	6.194ms	1	1	100.00
		chip_sw_mbx_smoketest	5.093m	4.831ms	1	1	100.00
		TOTAL			78	250	31.20

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.20602112315160428682014819509426231233143738800241637235565329673039681471043
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 132.699s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.49199354796327244345206369932689211977293902070469514934219415305782210534279
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 127.776s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.36429377053063404931894722094875363257698168692945670827784493849688514858662
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 137.745s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.24893932813696619127494899840092642847705238597143974436417807376271163128880
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 100.166s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.46439093170610669610724254762862210340363745298428960950962613295064106516345
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 96.061s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.74657109914166063806518655940200307993134512484700030624786137453322284502662
    Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.78058352103235915507320149321854084067034008179745655067400719571296464899659
    Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.100348028971889444277380075286998343688365249369362061444114355343485204290544
    Line 376, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.67290407228668982514210225557390248190139460924472677625181042640561619477357
    Line 377, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.100100360302290348601933800054380268936085038108099536860971840778329223660826
    Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 4 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.13857360371861231342131865962819795910190830097557046846387702606392156573436
Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12018.496190 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.496190 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.38601967418492028965681599432661419396048742862870765366812109368545682976265
Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12027.032269 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12027.032269 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.87241216342302974482094867259327223095669761671922073415536930666721274460847
Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12018.642896 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.642896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.48114641926332913349627209014013117116982691278104751581616988955929553078652
Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12026.539132 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.539132 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.103421495020238432888100571894504473359093421863695250088042307466566140032737
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.87477032253425679566770686447937519085507610156410408593880268223744833992858
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.46469215130452159894066010997816629557531024959599312693283973155172741207091
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.32672268102323133769659320121297991170941531459761566328894436258330145703419
Line 433, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20026.979888 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20026.979888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.51421919004785589877320772496788377641931540931498232707428968385135318137388
Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18018.469677 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.469677 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.76109359663736777955656173023361765594196779500371250690020078014450408842481
Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18018.564166 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.564166 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.29421472419254949010959654536519301758919373624425941762521045279410297717132
Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 10101.151192 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (6518520961653189694749619858405498101497506886008179923271077091861179166412077536607270321105686144983131012087511719986104462615152701243513295916588124 [0x7c75dde3aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3fa236d127f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 10101.151192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.29094236807455939976010809062444221961271376107687539020812927724988765574977
Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 8326.764828 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (11172918007494973598451198664831307569439868147368822914498848778761141314881748467065283260948752064568319407133656193402324452060869941843199928490613852 [0xd55415eaaae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35302a51b7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 8326.764828 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.110170891756749252777174111070918452728809307260893438852523781040861363160537
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3304.375571 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: 'h30480000  a_data: 'h315d4097  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h26  a_opcode: 'h1  a_user: 'h248de  d_param: 'h0  d_source: 'h26  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3304.375571 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.59027612494349785508144024588221803444135814591381540394228727079512176639898
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3432.461162 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: 'h30480000  a_data: 'hc78c61b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h26908  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3432.461162 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.12279477154954572790425122478739189460574018558913266724228525329212495820191
    Line 1369, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.38072849368603165128735174290027860262650751136391261573301885025119948653073
    Line 433, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4392.533413 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4392.533413 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.25410003411740711169059233792228742830724618122401738697113425241409622589615
    Line 640, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 7296.164888 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 7296.164888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.60316411629282785776088128427651459822935951663954135379223313106539644734148
    Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5174.656550 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5174.656550 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.49218640290926020046881239301588814019425955370203474296044339946140205364659
    Line 384, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 3480.736693 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 3480.736693 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.110198432467292585906633258322634874339844404653011175597332145948894683830894
    Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4190.674188 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4190.674188 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == * has 1 failures:
- Test chip_sw_rv_core_ibex_rnd has 1 failures.
  - 0.chip_sw_rv_core_ibex_rnd.62416461069179193393427242122109974141388407043225572742398137452698008845703
    Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_rnd/latest/run.log
```
  UVM_ERROR @ 4629.835940 us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == 0
  UVM_INFO @ 4629.835940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.50644326837065956616350181796284227016359732242825360958063140511631013101018
    Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6362.997628 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6362.997628 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.48452762739400389699491474267708554984561545530790497772319336468468638295891
    Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.70745171428517069661524023929192942734222498336625044859557046723178504355466
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3372.279812 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3372.279812 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.105309524390948310687777368397115339576749822142709008900007469304476632391414
    Line 377, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 15518.733432 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 15518.733432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.543230547606256164378211857678280281711327580382766422601520499595559347407
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.4736977997890473650662631407905006689604757378394607242154711483331155206524
    Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5006.011998 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5006.011998 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```