DMA Simulation Results

Thursday September 25 2025 16:02:37 UTC

GitHub Revision: 1fcae8b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	5.000s	5.115ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	7.000s	659.211us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	5.000s	681.591us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	1.000s	48.635us	1	1	100.00
V1	csr_rw	dma_csr_rw	1.000s	77.845us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	6.000s	532.201us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	4.000s	267.380us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	1.000s	17.867us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	1.000s	77.845us	1	1	100.00
		dma_csr_aliasing	4.000s	267.380us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.100m	20.716ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	7.517m	176.372ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	1.800m	55.662ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	1.800m	55.662ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	7.517m	176.372ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	6.817m	67.555ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	1.800m	55.662ms	1	1	100.00
V2	dma_abort	dma_abort	11.000s	3.171ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	3.117m	81.827ms	1	1	100.00
V2	alert_test	dma_alert_test	1.000s	24.418us	1	1	100.00
V2	intr_test	dma_intr_test	1.000s	18.127us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	3.000s	152.907us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	3.000s	152.907us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	1.000s	48.635us	1	1	100.00
		dma_csr_rw	1.000s	77.845us	1	1	100.00
		dma_csr_aliasing	4.000s	267.380us	1	1	100.00
		dma_same_csr_outstanding	2.000s	232.695us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	1.000s	48.635us	1	1	100.00
		dma_csr_rw	1.000s	77.845us	1	1	100.00
		dma_csr_aliasing	4.000s	267.380us	1	1	100.00
		dma_same_csr_outstanding	2.000s	232.695us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	25.000s	372.139us	1	1	100.00
		dma_generic_stress	6.817m	67.555ms	1	1	100.00
		dma_handshake_stress	1.800m	55.662ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	7.000s	1.184ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	3.000s	235.704us	1	1	100.00
		dma_sec_cm	1.000s	19.864us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	58.000s	5.485ms	1	1	100.00
		dma_longer_transfer	7.000s	3.007ms	1	1	100.00
		dma_stress_all_with_rand_reset	17.000s	4.542ms	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.54951275870060864983456209864495255609673791774158426895112806665910314873560
      Line 116, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4542447202ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4542447202ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---