EDN Simulation Results

Thursday September 25 2025 16:02:37 UTC

GitHub Revision: 1fcae8b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0.940s 25.461us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.810s 35.623us 1 1 100.00
V1 csr_rw edn_csr_rw 0.820s 34.649us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 2.540s 119.123us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 0.930s 81.179us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.190s 90.748us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.820s 34.649us 1 1 100.00
edn_csr_aliasing 0.930s 81.179us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.230s 112.381us 1 1 100.00
V2 csrng_commands edn_genbits 1.230s 112.381us 1 1 100.00
V2 genbits edn_genbits 1.230s 112.381us 1 1 100.00
V2 interrupts edn_intr 0.930s 31.601us 1 1 100.00
V2 alerts edn_alert 0.950s 195.218us 1 1 100.00
V2 errs edn_err 0.990s 46.308us 1 1 100.00
V2 disable edn_disable 0.860s 56.329us 1 1 100.00
edn_disable_auto_req_mode 0.880s 116.432us 1 1 100.00
V2 stress_all edn_stress_all 3.900s 357.517us 1 1 100.00
V2 intr_test edn_intr_test 0.810s 25.366us 1 1 100.00
V2 alert_test edn_alert_test 0.740s 38.481us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.120s 248.575us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.120s 248.575us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.810s 35.623us 1 1 100.00
edn_csr_rw 0.820s 34.649us 1 1 100.00
edn_csr_aliasing 0.930s 81.179us 1 1 100.00
edn_same_csr_outstanding 1.090s 39.674us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.810s 35.623us 1 1 100.00
edn_csr_rw 0.820s 34.649us 1 1 100.00
edn_csr_aliasing 0.930s 81.179us 1 1 100.00
edn_same_csr_outstanding 1.090s 39.674us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 4.260s 330.397us 1 1 100.00
edn_tl_intg_err 2.070s 156.657us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 0.970s 28.571us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 0.950s 195.218us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 4.260s 330.397us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 4.260s 330.397us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 4.260s 330.397us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 4.260s 330.397us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 0.950s 195.218us 1 1 100.00
edn_sec_cm 4.260s 330.397us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 0.950s 195.218us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.070s 156.657us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets