HMAC Simulation Results

Thursday September 25 2025 16:02:37 UTC

GitHub Revision: 1fcae8b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 10.490s 19.095ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.750s 44.985us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.760s 12.180us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 11.870s 1.604ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 6.000s 2.329ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.000s 51.010us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.760s 12.180us 1 1 100.00
hmac_csr_aliasing 6.000s 2.329ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 54.370s 1.364ms 1 1 100.00
V2 back_pressure hmac_back_pressure 10.770s 549.206us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 7.650s 294.989us 1 1 100.00
hmac_test_sha384_vectors 7.146m 53.204ms 1 1 100.00
hmac_test_sha512_vectors 18.610s 206.698us 1 1 100.00
hmac_test_hmac256_vectors 6.630s 415.737us 1 1 100.00
hmac_test_hmac384_vectors 7.140s 231.261us 1 1 100.00
hmac_test_hmac512_vectors 10.640s 350.153us 1 1 100.00
V2 burst_wr hmac_burst_wr 18.180s 2.709ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 16.777m 26.007ms 1 1 100.00
V2 error hmac_error 18.410s 4.325ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 48.170s 5.090ms 1 1 100.00
V2 save_and_restore hmac_smoke 10.490s 19.095ms 1 1 100.00
hmac_long_msg 54.370s 1.364ms 1 1 100.00
hmac_back_pressure 10.770s 549.206us 1 1 100.00
hmac_datapath_stress 16.777m 26.007ms 1 1 100.00
hmac_burst_wr 18.180s 2.709ms 1 1 100.00
hmac_stress_all 18.526m 26.675ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 10.490s 19.095ms 1 1 100.00
hmac_long_msg 54.370s 1.364ms 1 1 100.00
hmac_back_pressure 10.770s 549.206us 1 1 100.00
hmac_datapath_stress 16.777m 26.007ms 1 1 100.00
hmac_wipe_secret 48.170s 5.090ms 1 1 100.00
hmac_test_sha256_vectors 7.650s 294.989us 1 1 100.00
hmac_test_sha384_vectors 7.146m 53.204ms 1 1 100.00
hmac_test_sha512_vectors 18.610s 206.698us 1 1 100.00
hmac_test_hmac256_vectors 6.630s 415.737us 1 1 100.00
hmac_test_hmac384_vectors 7.140s 231.261us 1 1 100.00
hmac_test_hmac512_vectors 10.640s 350.153us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 10.490s 19.095ms 1 1 100.00
hmac_long_msg 54.370s 1.364ms 1 1 100.00
hmac_back_pressure 10.770s 549.206us 1 1 100.00
hmac_datapath_stress 16.777m 26.007ms 1 1 100.00
hmac_burst_wr 18.180s 2.709ms 1 1 100.00
hmac_error 18.410s 4.325ms 1 1 100.00
hmac_wipe_secret 48.170s 5.090ms 1 1 100.00
hmac_test_sha256_vectors 7.650s 294.989us 1 1 100.00
hmac_test_sha384_vectors 7.146m 53.204ms 1 1 100.00
hmac_test_sha512_vectors 18.610s 206.698us 1 1 100.00
hmac_test_hmac256_vectors 6.630s 415.737us 1 1 100.00
hmac_test_hmac384_vectors 7.140s 231.261us 1 1 100.00
hmac_test_hmac512_vectors 10.640s 350.153us 1 1 100.00
hmac_stress_all 18.526m 26.675ms 1 1 100.00
V2 stress_all hmac_stress_all 18.526m 26.675ms 1 1 100.00
V2 alert_test hmac_alert_test 0.850s 18.861us 1 1 100.00
V2 intr_test hmac_intr_test 0.680s 134.699us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.960s 162.959us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.960s 162.959us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.750s 44.985us 1 1 100.00
hmac_csr_rw 0.760s 12.180us 1 1 100.00
hmac_csr_aliasing 6.000s 2.329ms 1 1 100.00
hmac_same_csr_outstanding 1.890s 577.700us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.750s 44.985us 1 1 100.00
hmac_csr_rw 0.760s 12.180us 1 1 100.00
hmac_csr_aliasing 6.000s 2.329ms 1 1 100.00
hmac_same_csr_outstanding 1.890s 577.700us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.990s 72.380us 1 1 100.00
hmac_tl_intg_err 3.200s 142.961us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.200s 142.961us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 10.490s 19.095ms 1 1 100.00
V3 stress_reset hmac_stress_reset 2.060s 114.615us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 4.663m 5.214ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 3.660s 979.028us 1 1 100.00
TOTAL 28 28 100.00