I2C Simulation Results

Thursday September 25 2025 16:02:37 UTC

GitHub Revision: 1fcae8b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	26.290s	2.286ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	12.880s	5.410ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.040s	76.459us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.960s	21.263us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.140s	210.263us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.800s	238.283us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.070s	74.071us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.960s	21.263us	1	1	100.00
		i2c_csr_aliasing	1.800s	238.283us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.130s	59.280us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	3.663m	12.027ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	37.620s	4.931ms	1	1	100.00
V2	host_override	i2c_host_override	0.780s	47.098us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.219m	10.577ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	38.850s	7.743ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.530s	2.930ms	1	1	100.00
		i2c_host_fifo_fmt_empty	3.070s	880.296us	1	1	100.00
		i2c_host_fifo_reset_rx	3.010s	166.157us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.424m	3.531ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	7.450s	492.002us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.680s	67.572us	1	1	100.00
V2	target_glitch	i2c_target_glitch	2.370s	553.039us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	1.281m	74.871ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.530s	1.404ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	23.590s	1.527ms	1	1	100.00
		i2c_target_intr_smoke	6.490s	5.783ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.160s	192.461us	1	1	100.00
		i2c_target_fifo_reset_tx	1.280s	389.223us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	6.110s	16.936ms	1	1	100.00
		i2c_target_stress_rd	23.590s	1.527ms	1	1	100.00
		i2c_target_intr_stress_wr	1.774m	17.058ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.600s	1.442ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	3.220s	3.962ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	2.480s	2.277ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.410s	1.200ms	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.720s	372.885us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.770s	239.749us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	37.620s	4.931ms	1	1	100.00
		i2c_host_perf_precise	5.630s	192.419us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	7.450s	492.002us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.130s	121.029us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	1.970s	1.788ms	1	1	100.00
		i2c_target_nack_acqfull_addr	1.760s	526.207us	1	1	100.00
		i2c_target_nack_txstretch	1.500s	211.912us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	5.400s	369.058us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.700s	495.585us	1	1	100.00
V2	alert_test	i2c_alert_test	0.590s	15.808us	1	1	100.00
V2	intr_test	i2c_intr_test	0.960s	16.653us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.130s	111.838us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.130s	111.838us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.040s	76.459us	1	1	100.00
		i2c_csr_rw	0.960s	21.263us	1	1	100.00
		i2c_csr_aliasing	1.800s	238.283us	1	1	100.00
		i2c_same_csr_outstanding	1.330s	211.751us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.040s	76.459us	1	1	100.00
		i2c_csr_rw	0.960s	21.263us	1	1	100.00
		i2c_csr_aliasing	1.800s	238.283us	1	1	100.00
		i2c_same_csr_outstanding	1.330s	211.751us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.460s	512.085us	1	1	100.00
		i2c_sec_cm	0.870s	43.645us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.460s	512.085us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	19.090s	6.054ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	0.960s	45.538us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	12.750s	920.520us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.20898118566642747334392101255454554055333518723854497980081991798178051382252
      Line 96, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6054116541 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6054116541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.10833188544381012020719712192571023763610114938681413511327477293205434043425
      Line 90, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 920520008 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 920520008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.65594744145982219059062785605971305230957063828899714063849779928909075154679
      Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  59279759 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  59279759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.90714621337926128690679075805348870026649927389374641947596844456882328924207
      Line 142, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 12026648780 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @1912835
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.44465071136859934463499934510212570321635989160632401969884451349458939310505
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 553039354 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 553039354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.81493875177686531919564303706279880800798629526128209449609442514804344003176
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @  45537850 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @  45537850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---