KEYMGR Simulation Results

Thursday September 25 2025 16:02:37 UTC

GitHub Revision: 1fcae8b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.050s	563.526us	1	1	100.00
V1	random	keymgr_random	16.700s	954.053us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	0.900s	49.493us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	0.880s	25.436us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	9.440s	968.572us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	5.970s	719.094us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.180s	55.648us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	0.880s	25.436us	1	1	100.00
		keymgr_csr_aliasing	5.970s	719.094us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	4.330s	216.618us	1	1	100.00
V2	sideload	keymgr_sideload	3.670s	578.290us	1	1	100.00
		keymgr_sideload_kmac	2.470s	436.899us	1	1	100.00
		keymgr_sideload_aes	1.750s	69.916us	1	1	100.00
		keymgr_sideload_otbn	13.340s	1.560ms	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	1.530s	29.386us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	1.450s	56.793us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.760s	194.124us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	8.330s	1.938ms	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.130s	151.684us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	1.800s	91.196us	1	1	100.00
V2	stress_all	keymgr_stress_all	8.630s	8.522ms	1	1	100.00
V2	intr_test	keymgr_intr_test	0.670s	15.062us	1	1	100.00
V2	alert_test	keymgr_alert_test	0.840s	16.653us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	1.210s	96.133us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	1.210s	96.133us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	0.900s	49.493us	1	1	100.00
		keymgr_csr_rw	0.880s	25.436us	1	1	100.00
		keymgr_csr_aliasing	5.970s	719.094us	1	1	100.00
		keymgr_same_csr_outstanding	1.110s	25.219us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	0.900s	49.493us	1	1	100.00
		keymgr_csr_rw	0.880s	25.436us	1	1	100.00
		keymgr_csr_aliasing	5.970s	719.094us	1	1	100.00
		keymgr_same_csr_outstanding	1.110s	25.219us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	6.830s	2.068ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	6.830s	2.068ms	1	1	100.00
		keymgr_tl_intg_err	3.310s	134.060us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.190s	807.479us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.190s	807.479us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.190s	807.479us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.190s	807.479us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	6.750s	1.637ms	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	6.830s	2.068ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	6.830s	2.068ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	3.310s	134.060us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.190s	807.479us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	4.330s	216.618us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	16.700s	954.053us	1	1	100.00
		keymgr_csr_rw	0.880s	25.436us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	16.700s	954.053us	1	1	100.00
		keymgr_csr_rw	0.880s	25.436us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	16.700s	954.053us	1	1	100.00
		keymgr_csr_rw	0.880s	25.436us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	1.450s	56.793us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.130s	151.684us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.130s	151.684us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	16.700s	954.053us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	3.530s	377.558us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	6.830s	2.068ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	6.830s	2.068ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	6.830s	2.068ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.540s	77.531us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	1.450s	56.793us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	6.830s	2.068ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	6.830s	2.068ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	6.830s	2.068ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.540s	77.531us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.540s	77.531us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	6.830s	2.068ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.540s	77.531us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	6.830s	2.068ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.540s	77.531us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	4.410s	341.725us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			29	30	96.67

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.72307581238965727829863057212499515359112450162769986861491652690770521692178
      Line 475, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 341725249 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 341725249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---