| V1 |
smoke |
keymgr_dpe_smoke |
33.760s |
5.850ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
1.240s |
33.924us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
1.080s |
17.514us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
8.270s |
5.359ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
2.700s |
118.703us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
1.110s |
71.167us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
1.080s |
17.514us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
2.700s |
118.703us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
0.890s |
12.066us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
0.890s |
39.316us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
3.810s |
227.511us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
3.810s |
227.511us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
1.240s |
33.924us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.080s |
17.514us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
2.700s |
118.703us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
1.220s |
81.005us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
1.240s |
33.924us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.080s |
17.514us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
2.700s |
118.703us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
1.220s |
81.005us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
5.030s |
970.646us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
3.550s |
405.389us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
3.060s |
122.533us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
3.060s |
122.533us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
3.060s |
122.533us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
3.060s |
122.533us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
3.420s |
108.550us |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
5.030s |
970.646us |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
5.030s |
970.646us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |