MBX Simulation Results

Thursday September 25 2025 16:02:37 UTC

GitHub Revision: 1fcae8b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	mbx_smoke	mbx_smoke	40.000s	13.798ms	1	1	100.00
V1	csr_hw_reset	mbx_csr_hw_reset	1.000s	38.550us	1	1	100.00
V1	csr_rw	mbx_csr_rw	2.000s	24.965us	1	1	100.00
V1	csr_bit_bash	mbx_csr_bit_bash	4.000s	486.484us	1	1	100.00
V1	csr_aliasing	mbx_csr_aliasing	2.000s	31.864us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	mbx_csr_mem_rw_with_rand_reset	1.000s	50.691us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	mbx_csr_rw	2.000s	24.965us	1	1	100.00
		mbx_csr_aliasing	2.000s	31.864us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	mbx_stress	mbx_stress	3.000s	173.627us	0	1	0.00
V2	mbx_max_activity	mbx_stress_zero_delays	43.000s	4.805ms	1	1	100.00
V2	mbx_imbx_oob	mbx_imbx_oob	22.000s	7.781ms	1	1	100.00
V2	mbx_doe_intr_msg	mbx_doe_intr_msg	17.000s	535.913us	1	1	100.00
V2	alert_test	mbx_alert_test	2.000s	32.175us	1	1	100.00
V2	intr_test	mbx_intr_test	1.000s	109.767us	1	1	100.00
V2	tl_d_oob_addr_access	mbx_tl_errors	3.000s	81.179us	1	1	100.00
V2	tl_d_illegal_access	mbx_tl_errors	3.000s	81.179us	1	1	100.00
V2	tl_d_outstanding_access	mbx_csr_hw_reset	1.000s	38.550us	1	1	100.00
		mbx_csr_rw	2.000s	24.965us	1	1	100.00
		mbx_csr_aliasing	2.000s	31.864us	1	1	100.00
		mbx_same_csr_outstanding	2.000s	194.197us	1	1	100.00
V2	tl_d_partial_access	mbx_csr_hw_reset	1.000s	38.550us	1	1	100.00
		mbx_csr_rw	2.000s	24.965us	1	1	100.00
		mbx_csr_aliasing	2.000s	31.864us	1	1	100.00
		mbx_same_csr_outstanding	2.000s	194.197us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	mbx_tl_intg_err	2.000s	214.735us	1	1	100.00
		mbx_sec_cm	1.000s	16.513us	1	1	100.00
V2S		TOTAL			2	2	100.00
		TOTAL			15	16	93.75

Failure Buckets

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,287): Assertion ReadyAssertedWhenRead_A has failed has 1 failures:
  • Test mbx_stress has 1 failures.

    • 0.mbx_stress.80177191966298865666572367306674104262933956540260724563083937229334705993566
      Line 187, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_0.1/rtl/mbx_ombx.sv,287): (time 173626982 PS) Assertion tb.dut.u_ombx.ReadyAssertedWhenRead_A has failed
        UVM_ERROR @ 173626982 ps: (mbx_ombx.sv:287) [ASSERT FAILED] ReadyAssertedWhenRead_A
        UVM_INFO @ 173626982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---