RV_TIMER Simulation Results

Thursday September 25 2025 16:02:37 UTC

GitHub Revision: 1fcae8b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.700s	27.171us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.680s	12.355us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.770s	36.042us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.510s	529.839us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.720s	43.126us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.810s	17.205us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.770s	36.042us	1	1	100.00
		rv_timer_csr_aliasing	0.720s	43.126us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.200s	269.867us	0	1	0.00
V2	disabled	rv_timer_disabled	1.850s	3.417ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	8.486m	1.516s	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	8.486m	1.516s	1	1	100.00
V2	stress	rv_timer_stress_all	3.510s	7.456ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.810s	38.013us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.780s	21.491us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.750s	76.241us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.750s	76.241us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.680s	12.355us	1	1	100.00
		rv_timer_csr_rw	0.770s	36.042us	1	1	100.00
		rv_timer_csr_aliasing	0.720s	43.126us	1	1	100.00
		rv_timer_same_csr_outstanding	0.590s	20.242us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.680s	12.355us	1	1	100.00
		rv_timer_csr_rw	0.770s	36.042us	1	1	100.00
		rv_timer_csr_aliasing	0.720s	43.126us	1	1	100.00
		rv_timer_same_csr_outstanding	0.590s	20.242us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	1.130s	228.077us	1	1	100.00
		rv_timer_tl_intg_err	1.460s	110.226us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.460s	110.226us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.600s	12.313us	1	1	100.00
V3	max_value	rv_timer_max	0.600s	94.605us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	20.450s	14.425ms	1	1	100.00
V3		TOTAL			2	3	66.67
		TOTAL			17	19	89.47

Failure Buckets

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.23399594017823801954843428699045742405982841206441043169839507499670157399784
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @  94604753 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @  94604753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 1 failures:

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.57287441814996774010990566390295392904179416348253970895566175553712086407949
      Line 74, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 269866833 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x1c7a5f04) == 0x1
        UVM_INFO @ 269866833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---