SPI_DEVICE/1R1W Simulation Results

Thursday September 25 2025 16:02:37 UTC

GitHub Revision: 1fcae8b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	2.553m	27.491ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.400s	56.885us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.430s	317.227us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	8.730s	5.536ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.380s	4.187ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.410s	31.414us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.430s	317.227us	1	1	100.00
		spi_device_csr_aliasing	15.380s	4.187ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	15.580us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.030s	72.170us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.810s	28.937us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.910s	1.727us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.850s	6.709us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.190s	60.577us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.190s	60.577us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	14.420s	7.182ms	1	1	100.00
		spi_device_tpm_sts_read	0.920s	240.391us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	3.280s	746.880us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	14.330s	30.899ms	1	1	100.00
		spi_device_flash_all	22.510s	2.338ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.250s	97.718us	1	1	100.00
		spi_device_flash_all	22.510s	2.338ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.250s	97.718us	1	1	100.00
		spi_device_flash_all	22.510s	2.338ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	22.510s	2.338ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.630s	404.878us	1	1	100.00
		spi_device_flash_all	22.510s	2.338ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.630s	404.878us	1	1	100.00
		spi_device_flash_all	22.510s	2.338ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.630s	404.878us	1	1	100.00
		spi_device_flash_all	22.510s	2.338ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.630s	404.878us	1	1	100.00
		spi_device_flash_all	22.510s	2.338ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.630s	404.878us	1	1	100.00
		spi_device_flash_all	22.510s	2.338ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	2.210s	46.129us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	9.410s	6.816ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	9.410s	6.816ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	9.410s	6.816ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	13.820s	4.812ms	1	1	100.00
		spi_device_read_buffer_direct	3.010s	179.572us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	9.410s	6.816ms	1	1	100.00
		spi_device_flash_all	22.510s	2.338ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	22.510s	2.338ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	22.510s	2.338ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	8.890s	1.284ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	8.890s	1.284ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	2.553m	27.491ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.691m	78.658ms	1	1	100.00
V2	stress_all	spi_device_stress_all	30.620s	2.830ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.960s	24.919us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.890s	14.975us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.460s	249.162us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.460s	249.162us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.400s	56.885us	1	1	100.00
		spi_device_csr_rw	2.430s	317.227us	1	1	100.00
		spi_device_csr_aliasing	15.380s	4.187ms	1	1	100.00
		spi_device_same_csr_outstanding	3.380s	432.843us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.400s	56.885us	1	1	100.00
		spi_device_csr_rw	2.430s	317.227us	1	1	100.00
		spi_device_csr_aliasing	15.380s	4.187ms	1	1	100.00
		spi_device_same_csr_outstanding	3.380s	432.843us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.130s	189.989us	1	1	100.00
		spi_device_tl_intg_err	6.150s	375.668us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.150s	375.668us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	0.910s	54.285us	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.38997590475647119027116521528434269120997303047930098060343212100629111865883
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1077973 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[22])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1077973 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1077973 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[918])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.7752246466518758717655954749946261280165474320157387213237600103581595738016
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   4541229 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2f5e38 [1011110101111000111000] vs 0x0 [0])
        UVM_ERROR @   4630229 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd51c6d [110101010001110001101101] vs 0x0 [0])
        UVM_ERROR @   4677229 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5e2bad [10111100010101110101101] vs 0x0 [0])
        UVM_ERROR @   4686229 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x660250 [11001100000001001010000] vs 0x0 [0])
        UVM_ERROR @   4729229 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xaa6b9f [101010100110101110011111] vs 0x0 [0])