SPI_HOST Simulation Results

Thursday September 25 2025 16:02:37 UTC

GitHub Revision: 1fcae8b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	19.000s	1.736ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	101.652us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	1.000s	17.564us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	3.000s	797.495us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	43.778us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	33.971us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.000s	17.564us	1	1	100.00
		spi_host_csr_aliasing	2.000s	43.778us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	29.777us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	15.975us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	7.000s	49.477us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	8.000s	29.157us	1	1	100.00
		spi_host_error_cmd	6.000s	61.759us	1	1	100.00
		spi_host_event	22.000s	11.000ms	1	1	100.00
V2	clock_rate	spi_host_speed	12.000s	476.615us	1	1	100.00
V2	speed	spi_host_speed	12.000s	476.615us	1	1	100.00
V2	chip_select_timing	spi_host_speed	12.000s	476.615us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	10.000s	201.295us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	6.000s	21.288us	1	1	100.00
V2	cpol_cpha	spi_host_speed	12.000s	476.615us	1	1	100.00
V2	full_cycle	spi_host_speed	12.000s	476.615us	1	1	100.00
V2	duplex	spi_host_smoke	19.000s	1.736ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	19.000s	1.736ms	1	1	100.00
V2	stress_all	spi_host_stress_all	3.000s	157.992us	1	1	100.00
V2	spien	spi_host_spien	8.000s	432.070us	1	1	100.00
V2	stall	spi_host_status_stall	1.267m	37.181ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	4.000s	216.182us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	8.000s	29.157us	1	1	100.00
V2	alert_test	spi_host_alert_test	2.000s	39.805us	1	1	100.00
V2	intr_test	spi_host_intr_test	1.000s	18.335us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	1.000s	71.474us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	1.000s	71.474us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	101.652us	1	1	100.00
		spi_host_csr_rw	1.000s	17.564us	1	1	100.00
		spi_host_csr_aliasing	2.000s	43.778us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	377.942us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	101.652us	1	1	100.00
		spi_host_csr_rw	1.000s	17.564us	1	1	100.00
		spi_host_csr_aliasing	2.000s	43.778us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	377.942us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	1.000s	201.933us	1	1	100.00
		spi_host_sec_cm	2.000s	245.693us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	1.000s	201.933us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	4.783m	70.668ms	0	1	0.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:
  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.49916481677408896403922299863323437185838511929391057244478177422062050006055
      Line 184, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 70668027843 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 50000000ns spi_host_reg_block.status.active (addr=0x1047d694, Comparison=CompareOpEq, exp_data=0x0, call_count=24
        UVM_INFO @ 70668027843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---