SRAM_CTRL/MAIN Simulation Results

Thursday September 25 2025 16:02:37 UTC

GitHub Revision: 1fcae8b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	40.460s	1.306ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.750s	51.252us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	37.666us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.700s	463.545us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.720s	61.607us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.150s	5.792ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	37.666us	1	1	100.00
		sram_ctrl_csr_aliasing	0.720s	61.607us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.821m	5.978ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.772m	2.529ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	14.549m	22.696ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.947m	16.773ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	21.067m	288.121ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	1.179m	17.703ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	57.850s	33.156ms	1	1	100.00
V2	executable	sram_ctrl_executable	3.883m	20.248ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	12.960s	7.709ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.079m	23.122ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	26.920s	3.068ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	59.690s	825.639us	1	1	100.00
		sram_ctrl_throughput_w_readback	28.190s	798.663us	1	1	100.00
V2	regwen	sram_ctrl_regwen	8.802m	54.673ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.490s	1.461ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	42.347m	132.853ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.750s	23.358us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.840s	59.467us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.840s	59.467us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.750s	51.252us	1	1	100.00
		sram_ctrl_csr_rw	0.720s	37.666us	1	1	100.00
		sram_ctrl_csr_aliasing	0.720s	61.607us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.870s	34.154us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.750s	51.252us	1	1	100.00
		sram_ctrl_csr_rw	0.720s	37.666us	1	1	100.00
		sram_ctrl_csr_aliasing	0.720s	61.607us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.870s	34.154us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	19.460s	23.056ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.860s	682.290ns	0	1	0.00
		sram_ctrl_tl_intg_err	2.150s	316.686us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.860s	682.290ns	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.150s	316.686us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	8.802m	54.673ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	8.802m	54.673ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	37.666us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	3.883m	20.248ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	3.883m	20.248ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	3.883m	20.248ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	57.850s	33.156ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.890s	671.481us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	19.460s	23.056ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.030s	3.067ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	40.460s	1.306ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	40.460s	1.306ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	3.883m	20.248ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.860s	682.290ns	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	57.850s	33.156ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.860s	682.290ns	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.860s	682.290ns	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	40.460s	1.306ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.860s	682.290ns	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	30.620s	3.867ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(depth_o <= *'(Depth))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.22966925847216723879710111664122851887912864358817770654762579587683743331318
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @    682290 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @    682290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---