SRAM_CTRL/RET Simulation Results

Thursday September 25 2025 16:02:37 UTC

GitHub Revision: 1fcae8b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	5.210s	113.837us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.960s	44.004us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.020s	127.216us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.070s	182.040us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.720s	39.997us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.380s	127.107us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.020s	127.216us	1	1	100.00
		sram_ctrl_csr_aliasing	0.720s	39.997us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	9.040s	2.315ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.080s	378.261us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.880m	11.691ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.161m	13.921ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	24.420s	2.084ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	8.733m	14.695ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.940s	2.850ms	1	1	100.00
V2	executable	sram_ctrl_executable	1.398m	5.792ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	35.090s	7.329ms	1	1	100.00
		sram_ctrl_partial_access_b2b	6.469m	20.169ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	21.980s	410.556us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	0.970s	37.150us	1	1	100.00
		sram_ctrl_throughput_w_readback	50.000s	1.115ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	4.129m	2.452ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.980s	28.605us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	46.109m	162.503ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.930s	42.768us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.970s	68.439us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.970s	68.439us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.960s	44.004us	1	1	100.00
		sram_ctrl_csr_rw	1.020s	127.216us	1	1	100.00
		sram_ctrl_csr_aliasing	0.720s	39.997us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.850s	52.017us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.960s	44.004us	1	1	100.00
		sram_ctrl_csr_rw	1.020s	127.216us	1	1	100.00
		sram_ctrl_csr_aliasing	0.720s	39.997us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.850s	52.017us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.720s	219.891us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.710s	4.271us	0	1	0.00
		sram_ctrl_tl_intg_err	2.290s	585.913us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.710s	4.271us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.290s	585.913us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	4.129m	2.452ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	4.129m	2.452ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.020s	127.216us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	1.398m	5.792ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	1.398m	5.792ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	1.398m	5.792ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.940s	2.850ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.280s	68.431us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.720s	219.891us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.320s	150.745us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	5.210s	113.837us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	5.210s	113.837us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	1.398m	5.792ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.710s	4.271us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.940s	2.850ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.710s	4.271us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.710s	4.271us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	5.210s	113.837us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.710s	4.271us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	32.000s	4.194ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.113325428934334414783056906481782752654300083582116903337376833509303115926751
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4270785 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4270785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---