UART Simulation Results

Thursday September 25 2025 16:02:37 UTC

GitHub Revision: 1fcae8b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.320s	845.314us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.860s	25.131us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.730s	16.992us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.340s	585.497us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.660s	14.794us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.910s	17.453us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.730s	16.992us	1	1	100.00
		uart_csr_aliasing	0.660s	14.794us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	20.580s	71.480ms	1	1	100.00
V2	parity	uart_smoke	2.320s	845.314us	1	1	100.00
		uart_tx_rx	20.580s	71.480ms	1	1	100.00
V2	parity_error	uart_intr	19.140s	51.353ms	1	1	100.00
		uart_rx_parity_err	20.050s	13.248ms	1	1	100.00
V2	watermark	uart_tx_rx	20.580s	71.480ms	1	1	100.00
		uart_intr	19.140s	51.353ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.174m	62.402ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.373m	70.360ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	9.780s	78.672ms	1	1	100.00
V2	rx_frame_err	uart_intr	19.140s	51.353ms	1	1	100.00
V2	rx_break_err	uart_intr	19.140s	51.353ms	1	1	100.00
V2	rx_timeout	uart_intr	19.140s	51.353ms	1	1	100.00
V2	perf	uart_perf	4.076m	9.306ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.600s	4.165ms	1	1	100.00
V2	line_loopback	uart_loopback	2.600s	4.165ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	14.810s	18.613ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	7.950s	4.613ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	8.770s	8.311ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	8.960s	4.178ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	4.294m	68.742ms	1	1	100.00
V2	stress_all	uart_stress_all	1.745m	257.089ms	1	1	100.00
V2	alert_test	uart_alert_test	0.690s	61.414us	1	1	100.00
V2	intr_test	uart_intr_test	0.820s	31.412us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.540s	53.958us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.540s	53.958us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.860s	25.131us	1	1	100.00
		uart_csr_rw	0.730s	16.992us	1	1	100.00
		uart_csr_aliasing	0.660s	14.794us	1	1	100.00
		uart_same_csr_outstanding	0.820s	38.059us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.860s	25.131us	1	1	100.00
		uart_csr_rw	0.730s	16.992us	1	1	100.00
		uart_csr_aliasing	0.660s	14.794us	1	1	100.00
		uart_same_csr_outstanding	0.820s	38.059us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.000s	35.668us	1	1	100.00
		uart_tl_intg_err	1.090s	53.873us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.090s	53.873us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	31.500s	55.397ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.18330125857872612087858928932640890754176908226976296165357103454497766126827
      Line 74, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 17597099839 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0
        UVM_ERROR @ 17597112997 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 17597126155 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (232 [0xe8] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 17606244649 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 17606244649 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0