CHIP Simulation Results

Thursday September 25 2025 16:02:37 UTC

GitHub Revision: `1fcae8b`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.758m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.758m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.145m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	54.253s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	17.145s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.138m	5.834ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.138m	5.834ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.138m	5.834ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	30.900s	10.280us	0	1	0.00
		chip_sw_example_manufacturer	2.339m		0	1	0.00
		chip_sw_example_concurrency	4.863m	4.368ms	1	1	100.00
		chip_sw_uart_smoketest_signed	12.194s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	9.260s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	9.060s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	9.060s		0	1	0.00
V1	xbar_smoke	xbar_smoke	9.110s	12.825us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.668m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	14.821m	9.884ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.921m	4.382ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	13.500s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	12.433s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	13.141s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	14.397s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	2.820s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.820s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.726m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.784m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	1.871m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	1.871m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.821m	3.606ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.319m	3.746ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.706m	14.563ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.058s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	14.048s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.538m	7.702ms	0	1	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.781m	5.350ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	23.225m	18.027ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	23.225m	18.027ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	13.105s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.133m	4.485ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.133m	4.485ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	8.944m	18.018ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.632m	5.307ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	6.706m	5.027ms	1	1	100.00
		chip_sw_aes_idle	4.995m	4.338ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.682m	4.659ms	1	1	100.00
		chip_sw_kmac_idle	5.342m	5.300ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	12.580m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	14.226m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	12.938m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	12.500m	12.027ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	13.363s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.087s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.404s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.331s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.310s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	14.239s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.275s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	13.363s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.087s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.404s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.331s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.310s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	14.239s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.275s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	13.702s		0	1	0.00
		chip_sw_aes_enc_jitter_en	37.850s	10.140us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	40.630s	10.400us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	37.720s	10.100us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	43.770s	10.120us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.252s		0	1	0.00
		chip_sw_clkmgr_jitter	4.042m	5.532ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.208m	4.480ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	11.702s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	38.110s	10.140us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	38.620s	10.240us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	41.780s	10.360us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	37.920s	10.240us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	41.580s	10.380us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.848s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	15.453s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	13.307s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.189s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	35.770s	10.200us	0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	13.566m	15.553ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	6.133m	4.485ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	12.371s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	13.566m	15.553ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	12.639s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	14.660s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	13.085s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	12.431s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	11.599s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	35.770s	10.200us	0	1	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.706m	14.563ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	23.569m	20.027ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.457m	7.405ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	10.796m	8.483ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.421m	5.363ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	35.770s	10.200us	0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	12.287s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	17.023s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	35.770s	10.200us	0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	15.244s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	10.796m	8.483ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	13.681s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	12.234s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	13.327s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	12.738s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.591s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	12.101s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	17.023s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	11.680s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	15.835s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	11.680s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	11.680s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	11.680s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	7.773m	8.155ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	22.762s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	13.616s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	14.154s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	14.257s		0	1	0.00
		chip_sw_lc_ctrl_transition	11.680s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	7.100m	5.363ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	10.329m	15.453ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	14.972s		0	1	0.00
		chip_prim_tl_access	15.973m	20.270ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	13.363s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.087s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.404s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.331s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.310s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	14.239s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.275s		0	1	0.00
		chip_rv_dm_lc_disabled	6.538m	7.702ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.538m	5.143ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	37.850s	10.140us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.483m	3.520ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.995m	4.338ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.570m	4.275ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	40.630s	10.400us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.682m	4.659ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.588m	4.180ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.008m	4.412ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	43.770s	10.120us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	7.100m	5.363ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	11.680s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	30.930s	10.180us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.362m	3.902ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.342m	5.300ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.787s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.787s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	13.486s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.052m	4.202ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	14.004s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	7.100m	5.363ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	37.720s	10.100us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	13.167s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	13.702s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	6.706m	5.027ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	6.706m	5.027ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	6.706m	5.027ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.974m	6.478ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	10.329m	15.453ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	10.329m	15.453ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.837m	6.438ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.252s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	14.972s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	35.770s	10.200us	0	1	0.00
		chip_sw_data_integrity_escalation	1.871m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	11.680s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.974m	6.478ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.100m	5.363ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.837m	6.438ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.662m	4.084ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.974m	6.478ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.100m	5.363ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.837m	6.438ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.662m	4.084ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	11.680s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.549s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	15.835s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	22.762s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	13.616s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	14.154s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	14.257s		0	1	0.00
		chip_sw_lc_ctrl_transition	11.680s		0	1	0.00
		chip_prim_tl_access	15.973m	20.270ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	15.973m	20.270ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	11.845s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	14.574s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	15.453s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	13.702s		0	1	0.00
		chip_sw_aes_enc_jitter_en	37.850s	10.140us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	40.630s	10.400us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	37.720s	10.100us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	43.770s	10.120us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.252s		0	1	0.00
		chip_sw_clkmgr_jitter	4.042m	5.532ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	8.014m	8.571ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	8.014m	8.571ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	5.079m	5.201ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.315m	5.053ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.996m	5.783ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.051m	6.341ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.846m	5.788ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.593m	3.797ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.662m	4.084ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	23.569m	20.027ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	23.569m	20.027ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.942m	5.559ms	1	1	100.00
		chip_sw_aon_timer_smoketest	4.196m	3.992ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.202m	3.689ms	1	1	100.00
		chip_sw_csrng_smoketest	4.187m	4.888ms	1	1	100.00
		chip_sw_gpio_smoketest	3.377m	4.086ms	1	1	100.00
		chip_sw_hmac_smoketest	4.406m	3.932ms	1	1	100.00
		chip_sw_kmac_smoketest	4.705m	6.156ms	1	1	100.00
		chip_sw_otbn_smoketest	4.814m	5.416ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.952m	4.782ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.391m	5.929ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.960m	4.919ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.202m	3.200ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.586m	3.338ms	1	1	100.00
		chip_sw_uart_smoketest	4.041m	5.000ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	28.220s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	12.194s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.668m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	15.126s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	5.441m	5.604ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.193m	4.506ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.123m	4.726ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.308m	3.633ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	15.642s		0	1	0.00
		chip_rv_dm_lc_disabled	6.538m	7.702ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	13.693s		0	1	0.00
		chip_sw_lc_walkthrough_prod	14.382s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	13.310s		0	1	0.00
		chip_sw_lc_walkthrough_rma	15.136s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	15.642s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	11.971s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	12.239s		0	1	0.00
		rom_volatile_raw_unlock	12.554s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.619s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.467m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.702m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.802m	3.755ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.802m	3.755ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	9.060s		0	1	0.00
		chip_same_csr_outstanding	13.300s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	9.060s		0	1	0.00
		chip_same_csr_outstanding	13.300s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	33.880s	82.959us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.340s	11.279us	1	1	100.00
		xbar_smoke_large_delays	4.545m	2.299ms	1	1	100.00
		xbar_smoke_slow_rsp	6.037m	2.199ms	1	1	100.00
		xbar_random_zero_delays	1.326m	67.024us	1	1	100.00
		xbar_random_large_delays	24.074m	12.289ms	1	1	100.00
		xbar_random_slow_rsp	18.307m	6.347ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	59.980s	37.315us	1	1	100.00
		xbar_error_and_unmapped_addr	9.510s	9.770us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	2.482m	379.634us	1	1	100.00
		xbar_error_and_unmapped_addr	9.510s	9.770us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.180m	170.698us	1	1	100.00
		xbar_access_same_device_slow_rsp	26.567m	9.523ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	24.970s	63.225us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	19.960m	2.592ms	1	1	100.00
		xbar_stress_all_with_error	1.232m	62.727us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	32.480m	2.915ms	1	1	100.00
		xbar_stress_all_with_reset_error	23.785m	1.193ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.151s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	13.061s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	13.099s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	13.086s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	12.907s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	13.441s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	12.423s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	13.376s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	13.673s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	13.524s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	13.142s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.865s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	28.368s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.305m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.190m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	59.243s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	58.157s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.177m		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	46.579s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	43.143s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	53.721s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	44.716s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	51.782s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	46.164s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	38.485s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	39.673s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	39.609s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	28.653s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	14.896s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.840s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	14.022s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	19.799s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.330s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.776s		0	1	0.00
		rom_e2e_asm_init_dev	12.323s		0	1	0.00
		rom_e2e_asm_init_prod	12.058s		0	1	0.00
		rom_e2e_asm_init_prod_end	12.562s		0	1	0.00
		rom_e2e_asm_init_rma	11.831s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	12.607s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	12.708s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	12.369s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.396s		0	1	0.00
V2		TOTAL			63	205	30.73
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.604m	4.772ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.739m	4.997ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.575s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.673s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.441s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	13.278s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	35.770s	10.200us	0	1	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	15.325s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	19.191m	12.179ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	12.487s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.309s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.575s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.673s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.441s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.863s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.742s		0	1	0.00
		rom_e2e_jtag_inject_rma	12.063s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.598s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	23.183m	16.160ms	1	1	100.00
		chip_sw_entropy_src_kat_test	4.442m	5.462ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	3.362m	3.398ms	1	1	100.00
		chip_plic_all_irqs_0	10.251m	6.819ms	1	1	100.00
		chip_plic_all_irqs_10	11.348m	6.310ms	1	1	100.00
		chip_sw_dma_inline_hashing	5.502m	5.936ms	1	1	100.00
		chip_sw_dma_abort	4.106m	5.775ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.687s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	12.261s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.628s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	12.405s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.871s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.576s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.601s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.764s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.863s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.762s		0	1	0.00
		chip_sw_entropy_src_smoketest	3.828m	4.413ms	1	1	100.00
		chip_sw_mbx_smoketest	4.360m	5.135ms	1	1	100.00
		TOTAL			77	250	30.80

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.70382227834627847202125877684917295858290525074399541602386834718243226592520
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 129.574s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.91866924244196754087607931770502367945470173053536384691397713122824191391495
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 101.541s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.35961495512167671778821952981000375694295096526637897287513055471527489565131
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Target //sw/device/tests:sleep_pin_wake_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 92.815s, Critical Path: 0.03s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.30488381015948025861531185294068656358330401480046483503785057332084446696609
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 95.772s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.64262251956704601400398916383340781110566684938402817008845790566201338486574
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 94.679s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.37560464534084847265445953381911705983652304915386070878175657294091236682670
    Line 378, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.74355894229897491364323098862719282829103633586999118546481909174234322603130
    Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.21596131355121301183493110746761796133556100338682334543569264730691159820536
    Line 376, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.102030158716439366148889974721408414150198301930192120044155732625219534377318
    Line 376, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.55653186700652979277894133752921423164840615823743581798580750025912528274044
    Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 4 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.26078979180589944763025840709367519227733242152281197043125187216976936939172
Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12027.023112 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12027.023112 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.95839249947946522281761373699802043955643648258522339921976192812321421728144
Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12018.652474 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.652474 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.77414623371745005523753611581985157773362595349979330158645570487835309464877
Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12018.713154 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.713154 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.106278248341094146709151239194844633664021752044489928587326240287224497625811
Line 398, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12026.731202 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.731202 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.50780973855715711320172912245855379585008766980434959180929473488697091655820
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.87968057918735485551135688108203220017046039660507301209279942265879230174755
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.88022664980080553790674463108603362794164179564831596088356302376509040320227
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.14643078740643557821605251387055688799923203667803611345529945203138503787761
Line 413, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20026.796403 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20026.796403 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.83041568976614447068309135708811474455567084783590718866540376780346745341500
Line 384, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18026.863189 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18026.863189 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.39535153540839307808946617625528524069799647722535207468719987159944004122172
Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18018.494324 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.494324 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.104756225191732452628734318767329526813953258019608570149524186095997563180744
Line 403, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 5362.874408 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (1928930195112282616218560540265677916934460974387387951131421517512668521719839832807419127793874272439223242559118841518377501943818386907007978131774556 [0x24d46a15aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3a282dae47f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 5362.874408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.76276938147663162224928294833619511660627775936369266486512023982210422077965
Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 8155.238339 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (1599385952998965064516939229970972717586580100295289935216923528240874496860667906427269445593228941349270846007483589504174196713495204632302680336063580 [0x1e89a2bcaae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd398df124d7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 8155.238339 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.100823329069494259364398912098870524892486856716451345565976961863262604269695
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3606.013926 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: 'h30480000  a_data: 'h8604d847  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2  a_opcode: 'h1  a_user: 'h248d8  d_param: 'h0  d_source: 'h2  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3606.013926 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.109267096277537192640928118233973875044509315927918595350855690351535043536657
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3746.098345 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: 'h30480000  a_data: 'h1b62fbca  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1c  a_opcode: 'h0  a_user: 'h26931  d_param: 'h0  d_source: 'h1c  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3746.098345 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.62637823260087892887483733452678015402186907378592236947271321863345332123000
    Line 1376, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 0.chip_sw_all_escalation_resets.13986094721457765334656805663143665741767112023614894245272539864717689138847
    Line 408, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_FATAL @  10.200001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.90454795127407166580964888640929215476259227546350368640591154108311411097684
    Line 409, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4381.803546 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4381.803546 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.14304999873838784982792238329799607766585934012272333476805725715842076839855
    Line 626, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 8482.637487 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 8482.637487 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.3839961568807901396461266641203166506924506200689393937695145273022526845675
    Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5201.227896 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5201.227896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.74324585517091361195999967548802591264849344411883621477742490762298760514720
    Line 384, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 5053.225056 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 5053.225056 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.11933662992587518166341966391104877112317080369037758894578712102543449060740
    Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4485.478133 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4485.478133 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.101722974753677007769107300708414715002950269482971407079956410271499854608717
    Line 384, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6341.288842 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6341.288842 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.110067420251377290021342414500643985099475242221914434865059448627170508786596
    Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.89005630716810814835151367890449882980412870524719418209100663976929939734721
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3755.287812 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3755.287812 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.10046987667272235123008244325075448534988763182055303646988695563826020280577
    Line 374, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14562.770266 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14562.770266 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.102278437687321834866535512558027123271946567436678751680958254406743568815927
    Line 224, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 7702.041945 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x406e4 read out mismatch
  UVM_INFO @ 7702.041945 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.83238084774724081358360492400685808260712851019379790514318130383372247307779
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.70846564401108800599965571361195452525940346085741470321671518135088016524266
    Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5774.817768 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5774.817768 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```