DMA Simulation Results

Monday September 29 2025 16:05:45 UTC

GitHub Revision: 8780efb

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	5.000s	303.694us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	5.000s	965.444us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	4.000s	296.872us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	381.686us	1	1	100.00
V1	csr_rw	dma_csr_rw	2.000s	28.358us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	9.000s	1.311ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	6.000s	736.884us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	1.000s	145.787us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	2.000s	28.358us	1	1	100.00
		dma_csr_aliasing	6.000s	736.884us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	22.000s	1.754ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	1.250m	6.957ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	3.100m	59.962ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	3.100m	59.962ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	1.250m	6.957ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	8.717m	219.432ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	3.100m	59.962ms	1	1	100.00
V2	dma_abort	dma_abort	10.000s	3.437ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.467m	28.846ms	1	1	100.00
V2	alert_test	dma_alert_test	2.000s	13.854us	1	1	100.00
V2	intr_test	dma_intr_test	1.000s	13.723us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	3.000s	227.676us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	3.000s	227.676us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	381.686us	1	1	100.00
		dma_csr_rw	2.000s	28.358us	1	1	100.00
		dma_csr_aliasing	6.000s	736.884us	1	1	100.00
		dma_same_csr_outstanding	2.000s	141.371us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	381.686us	1	1	100.00
		dma_csr_rw	2.000s	28.358us	1	1	100.00
		dma_csr_aliasing	6.000s	736.884us	1	1	100.00
		dma_same_csr_outstanding	2.000s	141.371us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	10.000s	57.029us	1	1	100.00
		dma_generic_stress	8.717m	219.432ms	1	1	100.00
		dma_handshake_stress	3.100m	59.962ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	6.000s	889.779us	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	2.000s	78.216us	1	1	100.00
		dma_sec_cm	2.000s	46.176us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	1.267m	7.597ms	1	1	100.00
		dma_longer_transfer	8.000s	437.071us	1	1	100.00
		dma_stress_all_with_rand_reset	3.000s	429.330us	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.3645585512672876273625195935621685142790848384602740841035640657499064925597
      Line 88, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  429329826ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10007 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  429329826ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---