EDN Simulation Results

Monday September 29 2025 16:05:45 UTC

GitHub Revision: 8780efb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.910s	28.139us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.000s	34.997us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.770s	18.930us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	1.510s	61.317us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.030s	282.991us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.050s	40.951us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.770s	18.930us	1	1	100.00
		edn_csr_aliasing	1.030s	282.991us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.630s	54.081us	1	1	100.00
V2	csrng_commands	edn_genbits	1.630s	54.081us	1	1	100.00
V2	genbits	edn_genbits	1.630s	54.081us	1	1	100.00
V2	interrupts	edn_intr	0.950s	38.431us	1	1	100.00
V2	alerts	edn_alert	1.010s	339.209us	1	1	100.00
V2	errs	edn_err	1.070s	28.976us	1	1	100.00
V2	disable	edn_disable	0.880s	34.219us	1	1	100.00
		edn_disable_auto_req_mode	0.970s	43.231us	1	1	100.00
V2	stress_all	edn_stress_all	1.850s	206.659us	1	1	100.00
V2	intr_test	edn_intr_test	0.810s	31.119us	1	1	100.00
V2	alert_test	edn_alert_test	0.990s	20.210us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.730s	414.112us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.730s	414.112us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.000s	34.997us	1	1	100.00
		edn_csr_rw	0.770s	18.930us	1	1	100.00
		edn_csr_aliasing	1.030s	282.991us	1	1	100.00
		edn_same_csr_outstanding	0.980s	29.721us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.000s	34.997us	1	1	100.00
		edn_csr_rw	0.770s	18.930us	1	1	100.00
		edn_csr_aliasing	1.030s	282.991us	1	1	100.00
		edn_same_csr_outstanding	0.980s	29.721us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	5.180s	894.318us	1	1	100.00
		edn_tl_intg_err	1.900s	288.810us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.100s	18.790us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.010s	339.209us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	5.180s	894.318us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	5.180s	894.318us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	5.180s	894.318us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	5.180s	894.318us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.010s	339.209us	1	1	100.00
		edn_sec_cm	5.180s	894.318us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.010s	339.209us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.900s	288.810us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	14.000s	810.864us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00