HMAC Simulation Results

Monday September 29 2025 16:05:45 UTC

GitHub Revision: 8780efb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 4.370s 1.403ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.120s 192.303us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.890s 23.499us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.290s 1.482ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.940s 445.757us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 5.541m 45.988ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.890s 23.499us 1 1 100.00
hmac_csr_aliasing 5.940s 445.757us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 39.640s 4.430ms 1 1 100.00
V2 back_pressure hmac_back_pressure 12.120s 1.263ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.170s 595.216us 1 1 100.00
hmac_test_sha384_vectors 6.407m 21.553ms 1 1 100.00
hmac_test_sha512_vectors 19.670s 1.058ms 1 1 100.00
hmac_test_hmac256_vectors 5.980s 192.934us 1 1 100.00
hmac_test_hmac384_vectors 7.500s 939.037us 1 1 100.00
hmac_test_hmac512_vectors 9.940s 317.262us 1 1 100.00
V2 burst_wr hmac_burst_wr 3.780s 188.011us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 6.910s 549.222us 1 1 100.00
V2 error hmac_error 49.040s 1.357ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.117m 6.744ms 1 1 100.00
V2 save_and_restore hmac_smoke 4.370s 1.403ms 1 1 100.00
hmac_long_msg 39.640s 4.430ms 1 1 100.00
hmac_back_pressure 12.120s 1.263ms 1 1 100.00
hmac_datapath_stress 6.910s 549.222us 1 1 100.00
hmac_burst_wr 3.780s 188.011us 1 1 100.00
hmac_stress_all 3.746m 25.207ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 4.370s 1.403ms 1 1 100.00
hmac_long_msg 39.640s 4.430ms 1 1 100.00
hmac_back_pressure 12.120s 1.263ms 1 1 100.00
hmac_datapath_stress 6.910s 549.222us 1 1 100.00
hmac_wipe_secret 1.117m 6.744ms 1 1 100.00
hmac_test_sha256_vectors 8.170s 595.216us 1 1 100.00
hmac_test_sha384_vectors 6.407m 21.553ms 1 1 100.00
hmac_test_sha512_vectors 19.670s 1.058ms 1 1 100.00
hmac_test_hmac256_vectors 5.980s 192.934us 1 1 100.00
hmac_test_hmac384_vectors 7.500s 939.037us 1 1 100.00
hmac_test_hmac512_vectors 9.940s 317.262us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 4.370s 1.403ms 1 1 100.00
hmac_long_msg 39.640s 4.430ms 1 1 100.00
hmac_back_pressure 12.120s 1.263ms 1 1 100.00
hmac_datapath_stress 6.910s 549.222us 1 1 100.00
hmac_burst_wr 3.780s 188.011us 1 1 100.00
hmac_error 49.040s 1.357ms 1 1 100.00
hmac_wipe_secret 1.117m 6.744ms 1 1 100.00
hmac_test_sha256_vectors 8.170s 595.216us 1 1 100.00
hmac_test_sha384_vectors 6.407m 21.553ms 1 1 100.00
hmac_test_sha512_vectors 19.670s 1.058ms 1 1 100.00
hmac_test_hmac256_vectors 5.980s 192.934us 1 1 100.00
hmac_test_hmac384_vectors 7.500s 939.037us 1 1 100.00
hmac_test_hmac512_vectors 9.940s 317.262us 1 1 100.00
hmac_stress_all 3.746m 25.207ms 1 1 100.00
V2 stress_all hmac_stress_all 3.746m 25.207ms 1 1 100.00
V2 alert_test hmac_alert_test 0.610s 35.584us 1 1 100.00
V2 intr_test hmac_intr_test 0.710s 101.402us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.880s 184.852us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.880s 184.852us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.120s 192.303us 1 1 100.00
hmac_csr_rw 0.890s 23.499us 1 1 100.00
hmac_csr_aliasing 5.940s 445.757us 1 1 100.00
hmac_same_csr_outstanding 1.460s 395.950us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.120s 192.303us 1 1 100.00
hmac_csr_rw 0.890s 23.499us 1 1 100.00
hmac_csr_aliasing 5.940s 445.757us 1 1 100.00
hmac_same_csr_outstanding 1.460s 395.950us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.840s 40.020us 1 1 100.00
hmac_tl_intg_err 2.210s 334.170us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.210s 334.170us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 4.370s 1.403ms 1 1 100.00
V3 stress_reset hmac_stress_reset 1.530s 292.846us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.313m 20.319ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.220s 118.843us 1 1 100.00
TOTAL 28 28 100.00