I2C Simulation Results

Monday September 29 2025 16:05:45 UTC

GitHub Revision: 8780efb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	13.670s	4.195ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	5.770s	3.084ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.850s	46.993us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.700s	18.304us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.350s	120.553us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.340s	157.052us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.700s	19.220us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.700s	18.304us	1	1	100.00
		i2c_csr_aliasing	1.340s	157.052us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.950s	24.330us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	1.766m	10.378ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	27.700s	7.552ms	1	1	100.00
V2	host_override	i2c_host_override	0.780s	47.571us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	2.950m	36.697ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	31.380s	7.453ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.940s	462.148us	1	1	100.00
		i2c_host_fifo_fmt_empty	20.530s	1.017ms	1	1	100.00
		i2c_host_fifo_reset_rx	6.560s	730.107us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.619m	5.330ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	7.180s	2.403ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.740s	152.659us	1	1	100.00
V2	target_glitch	i2c_target_glitch	2.480s	1.020ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	6.655m	30.836ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.340s	2.118ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	12.500s	2.179ms	1	1	100.00
		i2c_target_intr_smoke	3.300s	3.703ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	0.900s	461.241us	1	1	100.00
		i2c_target_fifo_reset_tx	0.830s	221.481us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	5.813m	63.172ms	1	1	100.00
		i2c_target_stress_rd	12.500s	2.179ms	1	1	100.00
		i2c_target_intr_stress_wr	2.420s	4.710ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.330s	8.901ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	6.600s	3.598ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.600s	3.092ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	5.460s	10.387ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.890s	1.569ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.130s	378.335us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	27.700s	7.552ms	1	1	100.00
		i2c_host_perf_precise	2.930s	323.633us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	7.180s	2.403ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	0.780s	5.752us	0	1	0.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.210s	1.542ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.770s	564.353us	1	1	100.00
		i2c_target_nack_txstretch	1.250s	800.572us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	6.580s	232.803us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.600s	1.698ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.870s	16.466us	1	1	100.00
V2	intr_test	i2c_intr_test	0.850s	57.207us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.550s	54.881us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.550s	54.881us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.850s	46.993us	1	1	100.00
		i2c_csr_rw	0.700s	18.304us	1	1	100.00
		i2c_csr_aliasing	1.340s	157.052us	1	1	100.00
		i2c_same_csr_outstanding	0.850s	22.014us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.850s	46.993us	1	1	100.00
		i2c_csr_rw	0.700s	18.304us	1	1	100.00
		i2c_csr_aliasing	1.340s	157.052us	1	1	100.00
		i2c_same_csr_outstanding	0.850s	22.014us	1	1	100.00
V2		TOTAL			33	38	86.84
V2S	tl_intg_err	i2c_tl_intg_err	1.220s	164.823us	1	1	100.00
		i2c_sec_cm	0.830s	78.147us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.220s	164.823us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	3.760s	343.407us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.230s	153.067us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	21.470s	2.911ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			42	50	84.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.80583778267444130530121423540674119619668422045372794932008924328204881015937
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  24330184 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  24330184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.53602854879143070919655933841020156357683980473381798785356111890980832158469
      Line 104, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 10378439585 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 10378439585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.106818708765781850464838812992424505353416153680460890074996580056832479106380
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 1020071852 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 1020071852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.98406832473609629867726089277569169890542106525105458976024340316935561183328
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

            Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
        UVM_ERROR @ 153066525 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
        UVM_INFO @ 153066525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.84372695161745024471367289706534948309519747760874217040844189991502637454945
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10386832978 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10386832978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.62743519567505547959369468438598214323094960504753145406988600966368087678632
      Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 343407280 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 343407280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1142) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.7123510320468173934624506290807167737750688610707095273146270823358903161569
      Line 89, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2910879101 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 2910879101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:

  • Test i2c_target_tx_stretch_ctrl has 1 failures.

    • 0.i2c_target_tx_stretch_ctrl.112294527071082089330792030324775557862571512204969781841501426194653453326688
      Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest/run.log

        Error-[CNST-CIF] Constraints inconsistency failure
        src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
          Constraints are inconsistent and cannot be solved.
          Please check the inconsistent constraints being printed above and rewrite
          them.