KEYMGR Simulation Results

Monday September 29 2025 16:05:45 UTC

GitHub Revision: 8780efb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	1.620s	56.812us	1	1	100.00
V1	random	keymgr_random	1.730s	108.069us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.010s	40.211us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	0.980s	27.476us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	10.520s	4.192ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	6.180s	740.849us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.230s	110.982us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	0.980s	27.476us	1	1	100.00
		keymgr_csr_aliasing	6.180s	740.849us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	2.100s	134.640us	1	1	100.00
V2	sideload	keymgr_sideload	1.730s	38.261us	1	1	100.00
		keymgr_sideload_kmac	1.780s	67.441us	1	1	100.00
		keymgr_sideload_aes	6.170s	819.850us	1	1	100.00
		keymgr_sideload_otbn	1.730s	36.262us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	1.820s	75.013us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.330s	49.402us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	1.040s	40.317us	0	1	0.00
V2	invalid_sw_input	keymgr_sw_invalid_input	4.030s	563.484us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.600s	25.665us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.670s	84.987us	1	1	100.00
V2	stress_all	keymgr_stress_all	21.530s	3.542ms	1	1	100.00
V2	intr_test	keymgr_intr_test	0.730s	31.267us	1	1	100.00
V2	alert_test	keymgr_alert_test	0.740s	23.613us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	1.670s	129.437us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	1.670s	129.437us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.010s	40.211us	1	1	100.00
		keymgr_csr_rw	0.980s	27.476us	1	1	100.00
		keymgr_csr_aliasing	6.180s	740.849us	1	1	100.00
		keymgr_same_csr_outstanding	1.210s	213.380us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.010s	40.211us	1	1	100.00
		keymgr_csr_rw	0.980s	27.476us	1	1	100.00
		keymgr_csr_aliasing	6.180s	740.849us	1	1	100.00
		keymgr_same_csr_outstanding	1.210s	213.380us	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	6.600s	1.254ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	6.600s	1.254ms	1	1	100.00
		keymgr_tl_intg_err	2.470s	815.738us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.130s	220.511us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.130s	220.511us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.130s	220.511us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.130s	220.511us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	4.090s	441.476us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	6.600s	1.254ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	6.600s	1.254ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	2.470s	815.738us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.130s	220.511us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.100s	134.640us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.730s	108.069us	1	1	100.00
		keymgr_csr_rw	0.980s	27.476us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.730s	108.069us	1	1	100.00
		keymgr_csr_rw	0.980s	27.476us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.730s	108.069us	1	1	100.00
		keymgr_csr_rw	0.980s	27.476us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.330s	49.402us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.600s	25.665us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.600s	25.665us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.730s	108.069us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	6.790s	540.040us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	6.600s	1.254ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	6.600s	1.254ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	6.600s	1.254ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	5.550s	1.360ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.330s	49.402us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	6.600s	1.254ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	6.600s	1.254ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	6.600s	1.254ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	5.550s	1.360ms	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	5.550s	1.360ms	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	6.600s	1.254ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	5.550s	1.360ms	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	6.600s	1.254ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	5.550s	1.360ms	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	2.540s	658.279us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			28	30	93.33

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:

  • Test keymgr_kmac_rsp_err has 1 failures.

    • 0.keymgr_kmac_rsp_err.41327611437287832970415314281214762093333016203829644603154122265753616642186
      Line 248, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_kmac_rsp_err/latest/run.log

        UVM_ERROR @  40317353 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
        UVM_INFO @  40317353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.16740095080414645925361687192176653008780744433743146504847875670036294395854
      Line 94, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 658279288 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 658279288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---