KMAC/MASKED Simulation Results

Monday September 29 2025 16:05:45 UTC

GitHub Revision: 8780efb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	2.000s	240.982us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.070s	22.390us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.180s	27.023us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	9.970s	298.384us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.850s	1.072ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.240s	541.983us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.180s	27.023us	1	1	100.00
		kmac_csr_aliasing	3.850s	1.072ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.020s	21.759us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.290s	154.197us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.959m	7.537ms	1	1	100.00
V2	burst_write	kmac_burst_write	39.290s	6.580ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	26.980s	2.671ms	1	1	100.00
		kmac_test_vectors_sha3_256	23.434m	76.482ms	1	1	100.00
		kmac_test_vectors_sha3_384	19.140s	1.450ms	1	1	100.00
		kmac_test_vectors_sha3_512	0.960s	28.354us	0	1	0.00
		kmac_test_vectors_shake_128	3.761m	29.619ms	1	1	100.00
		kmac_test_vectors_shake_256	23.464m	17.276ms	1	1	100.00
		kmac_test_vectors_kmac	2.900s	396.909us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.360s	160.868us	1	1	100.00
V2	sideload	kmac_sideload	55.570s	3.630ms	1	1	100.00
V2	app	kmac_app	3.116m	26.700ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.270m	14.336ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.389m	13.657ms	1	1	100.00
V2	error	kmac_error	1.178m	4.905ms	1	1	100.00
V2	key_error	kmac_key_error	8.260s	5.834ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	5.430s	775.864us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.570s	40.545us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.650s	504.841us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	27.380s	4.207ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.700s	156.680us	1	1	100.00
V2	stress_all	kmac_stress_all	10.896m	10.991ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.020s	47.162us	1	1	100.00
V2	alert_test	kmac_alert_test	1.180s	57.360us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.100s	91.518us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.100s	91.518us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.070s	22.390us	1	1	100.00
		kmac_csr_rw	1.180s	27.023us	1	1	100.00
		kmac_csr_aliasing	3.850s	1.072ms	1	1	100.00
		kmac_same_csr_outstanding	1.360s	153.813us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.070s	22.390us	1	1	100.00
		kmac_csr_rw	1.180s	27.023us	1	1	100.00
		kmac_csr_aliasing	3.850s	1.072ms	1	1	100.00
		kmac_same_csr_outstanding	1.360s	153.813us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.940s	227.413us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.940s	227.413us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.940s	227.413us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.940s	227.413us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.020s	292.597us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.331m	16.823ms	1	1	100.00
		kmac_tl_intg_err	1.930s	209.685us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.930s	209.685us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.700s	156.680us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	2.000s	240.982us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	55.570s	3.630ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.940s	227.413us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.331m	16.823ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.331m	16.823ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.331m	16.823ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	2.000s	240.982us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.700s	156.680us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.331m	16.823ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.335m	62.576ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	2.000s	240.982us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.440m	7.314ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
  • Test kmac_test_vectors_sha3_512 has 1 failures.

    • 0.kmac_test_vectors_sha3_512.100890785331274158050571080670166980450797257324004857541053603473276735187093
      Line 75, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_512/latest/run.log

        UVM_ERROR @  28353614 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @  28353614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---