8780efb| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 30.000s | 1.948ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 4.000s | 17.639us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 2.000s | 20.285us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 4.000s | 303.202us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 1.000s | 142.029us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 2.000s | 29.390us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 2.000s | 20.285us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 1.000s | 142.029us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | mbx_stress | mbx_stress | 9.000s | 15.652us | 0 | 1 | 0.00 |
| V2 | mbx_max_activity | mbx_stress_zero_delays | 11.000s | 214.642us | 0 | 1 | 0.00 |
| V2 | mbx_imbx_oob | mbx_imbx_oob | 13.000s | 2.168ms | 0 | 1 | 0.00 |
| V2 | mbx_doe_intr_msg | mbx_doe_intr_msg | 17.000s | 4.424ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 6.000s | 28.935us | 1 | 1 | 100.00 |
| V2 | intr_test | mbx_intr_test | 4.000s | 14.166us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 6.000s | 37.939us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 6.000s | 37.939us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 4.000s | 17.639us | 1 | 1 | 100.00 |
| mbx_csr_rw | 2.000s | 20.285us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 1.000s | 142.029us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 1.000s | 72.246us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 4.000s | 17.639us | 1 | 1 | 100.00 |
| mbx_csr_rw | 2.000s | 20.285us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 1.000s | 142.029us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 1.000s | 72.246us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 8 | 62.50 | |||
| V2S | tl_intg_err | mbx_tl_intg_err | 4.000s | 268.893us | 1 | 1 | 100.00 |
| mbx_sec_cm | 7.000s | 42.145us | 1 | 1 | 100.00 | ||
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| TOTAL | 13 | 16 | 81.25 |
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 2 failures:
Test mbx_stress has 1 failures.
0.mbx_stress.99518205495998398656418453287488981388485519663748946285435360625265686866095
Line 86, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest/run.log
UVM_ERROR @ 15652000 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 15652000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test mbx_imbx_oob has 1 failures.
0.mbx_imbx_oob.76532218569663014944655179169283751962872558422649547834566864824799172383484
Line 95, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_imbx_oob/latest/run.log
UVM_ERROR @ 2167529579 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 2167529579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched has 1 failures:
0.mbx_stress_zero_delays.17374648211984906947726457501774860793161511486703987332836210970587697449429
Line 201, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress_zero_delays/latest/run.log
UVM_ERROR @ 214642390 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (2610411744 [0x9b97b8e0] vs 0 [0x0]) RDATA read data mismatched
UVM_INFO @ 214642390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---