OTBN Simulation Results

Monday September 29 2025 16:05:45 UTC

GitHub Revision: 8780efb

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 10.000s 43.794us 0 1 0.00
V1 single_binary otbn_single 6.000s 16.338us 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 3.000s 54.060us 1 1 100.00
V1 csr_rw otbn_csr_rw 4.000s 14.902us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 4.000s 268.492us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 4.000s 22.803us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 7.000s 68.059us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 4.000s 14.902us 1 1 100.00
otbn_csr_aliasing 4.000s 22.803us 1 1 100.00
V1 mem_walk otbn_mem_walk 21.000s 994.440us 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 16.000s 120.638us 1 1 100.00
V1 TOTAL 7 9 77.78
V2 reset_recovery otbn_reset 41.000s 420.923us 0 1 0.00
V2 multi_error otbn_multi_err 41.000s 642.337us 0 1 0.00
V2 back_to_back otbn_multi 29.000s 787.307us 0 1 0.00
V2 stress_all otbn_stress_all 1.450m 1.331ms 0 1 0.00
V2 lc_escalation otbn_escalate 6.000s 75.396us 0 1 0.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 6.000s 26.473us 0 1 0.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 6.000s 14.346us 0 1 0.00
V2 alert_test otbn_alert_test 5.000s 16.706us 1 1 100.00
V2 intr_test otbn_intr_test 3.000s 40.881us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 5.000s 806.094us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 5.000s 806.094us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 3.000s 54.060us 1 1 100.00
otbn_csr_rw 4.000s 14.902us 1 1 100.00
otbn_csr_aliasing 4.000s 22.803us 1 1 100.00
otbn_same_csr_outstanding 3.000s 15.216us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 3.000s 54.060us 1 1 100.00
otbn_csr_rw 4.000s 14.902us 1 1 100.00
otbn_csr_aliasing 4.000s 22.803us 1 1 100.00
otbn_same_csr_outstanding 3.000s 15.216us 1 1 100.00
V2 TOTAL 4 11 36.36
V2S mem_integrity otbn_imem_err 5.000s 34.821us 0 1 0.00
otbn_dmem_err 6.000s 44.617us 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 29.000s 217.036us 0 1 0.00
otbn_controller_ispr_rdata_err 7.000s 220.987us 0 1 0.00
otbn_mac_bignum_acc_err 7.000s 54.716us 0 1 0.00
otbn_urnd_err 11.000s 60.116us 1 1 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 5.000s 43.085us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 5.000s 15.954us 1 1 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 5.000s 27.125us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 8.633m 3.259ms 1 1 100.00
otbn_tl_intg_err 15.000s 218.557us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 6.000s 39.282us 0 1 0.00
V2S prim_fsm_check otbn_sec_cm 8.633m 3.259ms 1 1 100.00
V2S prim_count_check otbn_sec_cm 8.633m 3.259ms 1 1 100.00
V2S sec_cm_mem_scramble otbn_smoke 10.000s 43.794us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 6.000s 44.617us 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 5.000s 34.821us 0 1 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 15.000s 218.557us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 6.000s 75.396us 0 1 0.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 5.000s 34.821us 0 1 0.00
otbn_dmem_err 6.000s 44.617us 0 1 0.00
otbn_zero_state_err_urnd 6.000s 26.473us 0 1 0.00
otbn_illegal_mem_acc 5.000s 43.085us 1 1 100.00
otbn_sec_cm 8.633m 3.259ms 1 1 100.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 8.633m 3.259ms 1 1 100.00
V2S sec_cm_scramble_key_sideload otbn_single 6.000s 16.338us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 5.000s 34.821us 0 1 0.00
otbn_dmem_err 6.000s 44.617us 0 1 0.00
otbn_zero_state_err_urnd 6.000s 26.473us 0 1 0.00
otbn_illegal_mem_acc 5.000s 43.085us 1 1 100.00
otbn_sec_cm 8.633m 3.259ms 1 1 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 8.633m 3.259ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 6.000s 75.396us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 5.000s 34.821us 0 1 0.00
otbn_dmem_err 6.000s 44.617us 0 1 0.00
otbn_zero_state_err_urnd 6.000s 26.473us 0 1 0.00
otbn_illegal_mem_acc 5.000s 43.085us 1 1 100.00
otbn_sec_cm 8.633m 3.259ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 8.633m 3.259ms 1 1 100.00
V2S sec_cm_data_reg_sw_sca otbn_single 6.000s 16.338us 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 4.000s 32.354us 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 7.000s 46.786us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 41.000s 635.633us 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 41.000s 635.633us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 8.000s 79.147us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 8.633m 3.259ms 1 1 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 8.633m 3.259ms 1 1 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 7.000s 184.266us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 8.633m 3.259ms 1 1 100.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 8.633m 3.259ms 1 1 100.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 12.000s 174.399us 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 12.000s 174.399us 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 16.000s 70.557us 0 1 0.00
V2S sec_cm_data_mem_sec_wipe otbn_single 6.000s 16.338us 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 6.000s 16.338us 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 6.000s 16.338us 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 29.000s 787.307us 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 6.000s 16.338us 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 6.000s 16.338us 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 7.000s 20.823us 0 1 0.00
V2S sec_cm_key_sideload otbn_single 6.000s 16.338us 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 8.633m 3.259ms 1 1 100.00
V2S TOTAL 7 20 35.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 1.250m 385.706us 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 18 41 43.90

Failure Buckets