RV_TIMER Simulation Results

Monday September 29 2025 16:05:45 UTC

GitHub Revision: 8780efb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.910s	84.052us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.760s	17.286us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.760s	16.815us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.470s	174.903us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.720s	30.966us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.010s	47.163us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.760s	16.815us	1	1	100.00
		rv_timer_csr_aliasing	0.720s	30.966us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.760s	135.292us	0	1	0.00
V2	disabled	rv_timer_disabled	2.410s	3.470ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	7.900s	5.782ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	7.900s	5.782ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.920s	2.140ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.740s	26.202us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.650s	100.190us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.100s	121.560us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.100s	121.560us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.760s	17.286us	1	1	100.00
		rv_timer_csr_rw	0.760s	16.815us	1	1	100.00
		rv_timer_csr_aliasing	0.720s	30.966us	1	1	100.00
		rv_timer_same_csr_outstanding	0.830s	37.128us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.760s	17.286us	1	1	100.00
		rv_timer_csr_rw	0.760s	16.815us	1	1	100.00
		rv_timer_csr_aliasing	0.720s	30.966us	1	1	100.00
		rv_timer_same_csr_outstanding	0.830s	37.128us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	1.110s	177.314us	1	1	100.00
		rv_timer_tl_intg_err	0.920s	44.522us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	0.920s	44.522us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.790s	263.334us	0	1	0.00
V3	max_value	rv_timer_max	0.780s	204.652us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	12.040s	9.562ms	1	1	100.00
V3		TOTAL			1	3	33.33
		TOTAL			16	19	84.21

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.23657781024377540281609933834240689596596557590791536065325614170385106921053
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @ 263334314 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x538fb04) == 0x1
        UVM_INFO @ 263334314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.85788549011415419158745441372139970461466213989776451070003470924739581269206
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 135292408 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x9994dd04) == 0x1
        UVM_INFO @ 135292408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.89817532703169657087869952700036677896225164334966954237722535946520146882650
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @ 204652164 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 204652164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---