SPI_DEVICE/1R1W Simulation Results

Monday September 29 2025 16:05:45 UTC

GitHub Revision: 8780efb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	4.734m	187.516ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.910s	20.984us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.050s	35.348us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	25.330s	7.228ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.400s	1.797ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.020s	159.232us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.050s	35.348us	1	1	100.00
		spi_device_csr_aliasing	16.400s	1.797ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.620s	32.766us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.110s	115.889us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.960s	18.609us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.980s	4.492us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.940s	3.523us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.260s	68.387us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.260s	68.387us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	0.850s	12.610us	1	1	100.00
		spi_device_tpm_sts_read	1.110s	109.676us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	10.160s	5.418ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.650s	1.153ms	1	1	100.00
		spi_device_flash_all	35.290s	12.958ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	5.530s	1.002ms	1	1	100.00
		spi_device_flash_all	35.290s	12.958ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	5.530s	1.002ms	1	1	100.00
		spi_device_flash_all	35.290s	12.958ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	35.290s	12.958ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.350s	636.147us	1	1	100.00
		spi_device_flash_all	35.290s	12.958ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.350s	636.147us	1	1	100.00
		spi_device_flash_all	35.290s	12.958ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.350s	636.147us	1	1	100.00
		spi_device_flash_all	35.290s	12.958ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.350s	636.147us	1	1	100.00
		spi_device_flash_all	35.290s	12.958ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.350s	636.147us	1	1	100.00
		spi_device_flash_all	35.290s	12.958ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	13.040s	27.569ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	26.870s	55.702ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	26.870s	55.702ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	26.870s	55.702ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	25.710s	4.391ms	1	1	100.00
		spi_device_read_buffer_direct	3.890s	547.559us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	26.870s	55.702ms	1	1	100.00
		spi_device_flash_all	35.290s	12.958ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	35.290s	12.958ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	35.290s	12.958ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	10.720s	1.324ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	10.720s	1.324ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	4.734m	187.516ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	27.130s	4.412ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.151m	6.073ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.760s	12.790us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.660s	13.103us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	1.570s	25.855us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	1.570s	25.855us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.910s	20.984us	1	1	100.00
		spi_device_csr_rw	1.050s	35.348us	1	1	100.00
		spi_device_csr_aliasing	16.400s	1.797ms	1	1	100.00
		spi_device_same_csr_outstanding	2.880s	62.415us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.910s	20.984us	1	1	100.00
		spi_device_csr_rw	1.050s	35.348us	1	1	100.00
		spi_device_csr_aliasing	16.400s	1.797ms	1	1	100.00
		spi_device_same_csr_outstanding	2.880s	62.415us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.160s	90.967us	1	1	100.00
		spi_device_tl_intg_err	15.360s	1.008ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	15.360s	1.008ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.820s	1.120ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.16036281995649300091205324243815943825438335119442655639802796707065470783430
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2639848 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[17])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2639848 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2639848 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[913])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.111801731249139185061779278002372599340999446492736066342528284511632261824613
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1184086 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd3e180 [110100111110000110000000] vs 0x0 [0])
        UVM_ERROR @   1213086 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x41b7b1 [10000011011011110110001] vs 0x0 [0])
        UVM_ERROR @   1278086 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x84baf9 [100001001011101011111001] vs 0x0 [0])
        UVM_ERROR @   1322086 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x915d0 [10010001010111010000] vs 0x0 [0])
        UVM_ERROR @   1378086 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe214b [11100010000101001011] vs 0x0 [0])