SRAM_CTRL/MAIN Simulation Results

Monday September 29 2025 16:05:45 UTC

GitHub Revision: 8780efb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	8.420s	1.053ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.850s	16.623us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.660s	22.353us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.510s	251.699us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.900s	28.046us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	7.500s	10.004ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.660s	22.353us	1	1	100.00
		sram_ctrl_csr_aliasing	0.900s	28.046us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	2.075m	22.567ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	47.430s	977.405us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	multiple_keys	sram_ctrl_multiple_keys	8.626m	39.551ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.197m	2.425ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	32.109m	221.328ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.138m	26.925ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	40.250s	19.568ms	1	1	100.00
V2	executable	sram_ctrl_executable	6.593m	64.490ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	18.210s	4.766ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.956m	18.595ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	24.930s	1.470ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	31.800s	825.050us	1	1	100.00
		sram_ctrl_throughput_w_readback	28.210s	3.371ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	10.310m	73.110ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.810s	695.579us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	34.772m	134.041ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.830s	21.538us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.960s	89.357us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.960s	89.357us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.850s	16.623us	1	1	100.00
		sram_ctrl_csr_rw	0.660s	22.353us	1	1	100.00
		sram_ctrl_csr_aliasing	0.900s	28.046us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.720s	17.187us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.850s	16.623us	1	1	100.00
		sram_ctrl_csr_rw	0.660s	22.353us	1	1	100.00
		sram_ctrl_csr_aliasing	0.900s	28.046us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.720s	17.187us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	18.150s	14.786ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.890s	3.357us	0	1	0.00
		sram_ctrl_tl_intg_err	2.490s	257.497us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.890s	3.357us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.490s	257.497us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	10.310m	73.110ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	10.310m	73.110ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.660s	22.353us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	6.593m	64.490ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	6.593m	64.490ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	6.593m	64.490ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	40.250s	19.568ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	6.750s	1.361ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	18.150s	14.786ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.020s	2.005ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	8.420s	1.053ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	8.420s	1.053ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	6.593m	64.490ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.890s	3.357us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	40.250s	19.568ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.890s	3.357us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.890s	3.357us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	8.420s	1.053ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.890s	3.357us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	33.970s	16.283ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.39218306881081441869339477772263041179056834948511389040882811001395341354060
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3356524 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3356524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (sram_ctrl_base_vseq.sv:168) [sram_ctrl_common_vseq] Timed out waiting for initialization done has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.sram_ctrl_csr_mem_rw_with_rand_reset.73070236913139631521122453914965548273163185548509911978579044916039892326109
      Line 93, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_FATAL @ 10004323271 ps: (sram_ctrl_base_vseq.sv:168) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done
        UVM_INFO @ 10004323271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---