SRAM_CTRL/RET Simulation Results

Monday September 29 2025 16:05:45 UTC

GitHub Revision: 8780efb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	15.230s	181.296us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.820s	42.565us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.900s	12.244us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.220s	163.318us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.720s	14.640us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.330s	42.604us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.900s	12.244us	1	1	100.00
		sram_ctrl_csr_aliasing	0.720s	14.640us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.990s	921.659us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.350s	290.277us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.958m	60.672ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.754m	4.803ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	58.470s	5.406ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	8.643m	14.829ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	4.830s	1.995ms	1	1	100.00
V2	executable	sram_ctrl_executable	8.111m	2.431ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	34.770s	681.271us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.296m	14.954ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	6.580s	122.276us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	10.840s	89.310us	1	1	100.00
		sram_ctrl_throughput_w_readback	13.780s	343.405us	1	1	100.00
V2	regwen	sram_ctrl_regwen	3.330m	1.461ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.790s	34.079us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	13.554m	5.253ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.000s	24.050us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.550s	37.392us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.550s	37.392us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.820s	42.565us	1	1	100.00
		sram_ctrl_csr_rw	0.900s	12.244us	1	1	100.00
		sram_ctrl_csr_aliasing	0.720s	14.640us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.920s	42.757us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.820s	42.565us	1	1	100.00
		sram_ctrl_csr_rw	0.900s	12.244us	1	1	100.00
		sram_ctrl_csr_aliasing	0.720s	14.640us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.920s	42.757us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.390s	1.683ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.930s	24.205us	0	1	0.00
		sram_ctrl_tl_intg_err	2.330s	681.122us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.930s	24.205us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.330s	681.122us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	3.330m	1.461ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	3.330m	1.461ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.900s	12.244us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	8.111m	2.431ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	8.111m	2.431ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	8.111m	2.431ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	4.830s	1.995ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.240s	34.559us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.390s	1.683ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.280s	120.414us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	15.230s	181.296us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	15.230s	181.296us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	8.111m	2.431ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.930s	24.205us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	4.830s	1.995ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.930s	24.205us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.930s	24.205us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	15.230s	181.296us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.930s	24.205us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	30.200s	257.469us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.48344224074170137372600670299589454887415326383123732262554377809654599937498
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  34558648 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  34558648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.8056390655215960901936782623098689048968480588304238284984346500358450293831
      Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  24205376 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  24205376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---