UART Simulation Results

Monday September 29 2025 16:05:45 UTC

GitHub Revision: 8780efb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.510s	657.046us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.830s	19.954us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.660s	41.196us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.030s	63.165us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.800s	15.384us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.880s	31.144us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.660s	41.196us	1	1	100.00
		uart_csr_aliasing	0.800s	15.384us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	13.690s	11.623ms	1	1	100.00
V2	parity	uart_smoke	1.510s	657.046us	1	1	100.00
		uart_tx_rx	13.690s	11.623ms	1	1	100.00
V2	parity_error	uart_intr	1.252m	74.377ms	1	1	100.00
		uart_rx_parity_err	29.780s	128.897ms	1	1	100.00
V2	watermark	uart_tx_rx	13.690s	11.623ms	1	1	100.00
		uart_intr	1.252m	74.377ms	1	1	100.00
V2	fifo_full	uart_fifo_full	20.140s	128.374ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	9.640s	16.389ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	21.310s	18.164ms	1	1	100.00
V2	rx_frame_err	uart_intr	1.252m	74.377ms	1	1	100.00
V2	rx_break_err	uart_intr	1.252m	74.377ms	1	1	100.00
V2	rx_timeout	uart_intr	1.252m	74.377ms	1	1	100.00
V2	perf	uart_perf	10.859m	17.635ms	1	1	100.00
V2	sys_loopback	uart_loopback	10.900s	9.677ms	1	1	100.00
V2	line_loopback	uart_loopback	10.900s	9.677ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	6.710s	5.509ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	5.120s	3.789ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	4.450s	1.273ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	3.980s	7.125ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.180m	59.577ms	1	1	100.00
V2	stress_all	uart_stress_all	51.430s	162.313ms	1	1	100.00
V2	alert_test	uart_alert_test	0.820s	21.042us	1	1	100.00
V2	intr_test	uart_intr_test	0.590s	14.556us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.230s	65.979us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.230s	65.979us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.830s	19.954us	1	1	100.00
		uart_csr_rw	0.660s	41.196us	1	1	100.00
		uart_csr_aliasing	0.800s	15.384us	1	1	100.00
		uart_same_csr_outstanding	0.960s	60.648us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.830s	19.954us	1	1	100.00
		uart_csr_rw	0.660s	41.196us	1	1	100.00
		uart_csr_aliasing	0.800s	15.384us	1	1	100.00
		uart_same_csr_outstanding	0.960s	60.648us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.210s	61.199us	1	1	100.00
		uart_tl_intg_err	1.040s	1.984ms	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.040s	1.984ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	21.790s	8.943ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00