CHIP Simulation Results

Monday September 29 2025 16:05:45 UTC

GitHub Revision: `8780efb`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.648m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.648m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	37.064s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	33.289s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	26.925s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.689m	5.405ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.689m	5.405ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.689m	5.405ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	31.870s	10.220us	0	1	0.00
		chip_sw_example_manufacturer	2.293m		0	1	0.00
		chip_sw_example_concurrency	4.388m	3.612ms	1	1	100.00
		chip_sw_uart_smoketest_signed	12.297s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	14.820s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	9.090s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	9.090s		0	1	0.00
V1	xbar_smoke	xbar_smoke	8.730s	12.003us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.311m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	12.831m	7.893ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.793m	4.701ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	11.989s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	12.821s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	11.903s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	12.309s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.040s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.040s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.092m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.858m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.131m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.131m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.416m	4.949ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.404m	5.427ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	5.048m	13.959ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	13.174s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.706s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	12.554m	16.015ms	0	1	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	7.136m	6.473ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	23.589m	18.019ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	23.589m	18.019ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.445s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.401m	3.459ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.401m	3.459ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	6.066m	18.027ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.203m	4.615ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	6.471m	5.482ms	1	1	100.00
		chip_sw_aes_idle	4.858m	5.026ms	1	1	100.00
		chip_sw_hmac_enc_idle	6.558m	6.059ms	1	1	100.00
		chip_sw_kmac_idle	3.691m	3.411ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	14.978m	12.018ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	12.971m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	13.191m	11.691ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	12.867m	12.027ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	12.025s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.351s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.680s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.668s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.997s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.762s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.010s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	12.025s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.351s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.680s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.668s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.997s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.762s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.010s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.971s		0	1	0.00
		chip_sw_aes_enc_jitter_en	43.970s	10.140us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	37.100s	10.200us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	44.810s	10.100us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	52.670s	10.400us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.043s		0	1	0.00
		chip_sw_clkmgr_jitter	3.672m	4.831ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.059m	5.092ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	12.060s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	41.750s	10.260us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	37.590s	10.380us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	39.030s	10.200us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	37.400s	10.280us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	38.590s	10.320us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.919s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	15.968s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	14.578s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.385s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	20.725m	15.219ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.217m	10.796ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.401m	3.459ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.572s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.217m	10.796ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	15.648s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	13.925s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	13.428s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	19.726s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	12.071s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	20.725m	15.219ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	5.048m	13.959ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	26.808m	20.018ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.218m	9.810ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	9.151m	7.846ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.712m	3.948ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	20.725m	15.219ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	12.361s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	12.313s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	20.725m	15.219ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	12.637s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	9.151m	7.846ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	14.444s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	14.497s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	12.861s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	13.493s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	12.892s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	13.305s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	12.313s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	11.908s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	21.404s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	11.908s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	11.908s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	11.908s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.853m	5.965ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	17.831s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	14.812s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	17.653s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	14.526s		0	1	0.00
		chip_sw_lc_ctrl_transition	11.908s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.442m	7.173ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	9.908m	13.619ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	14.116s		0	1	0.00
		chip_prim_tl_access	6.013m	8.875ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	12.025s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.351s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.680s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.668s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.997s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.762s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.010s		0	1	0.00
		chip_rv_dm_lc_disabled	12.554m	16.015ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.153m	4.448ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	43.970s	10.140us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.046m	3.576ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.858m	5.026ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.824m	4.499ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	37.100s	10.200us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	6.558m	6.059ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.113m	5.759ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.716m	4.999ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	52.670s	10.400us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.442m	7.173ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	11.908s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	34.030s	10.260us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.054m	4.110ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.691m	3.411ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.628s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.628s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	15.061s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.405m	3.779ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	13.084s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.442m	7.173ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	44.810s	10.100us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	13.361s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	11.971s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	6.471m	5.482ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	6.471m	5.482ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	6.471m	5.482ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.115m	4.744ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.908m	13.619ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.908m	13.619ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.952m	9.040ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.043s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	14.116s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	20.725m	15.219ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.131m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	11.908s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.115m	4.744ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.442m	7.173ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.952m	9.040ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.782m	5.495ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.115m	4.744ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.442m	7.173ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.952m	9.040ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.782m	5.495ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	11.908s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.466s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	21.404s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	17.831s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	14.812s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	17.653s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	14.526s		0	1	0.00
		chip_sw_lc_ctrl_transition	11.908s		0	1	0.00
		chip_prim_tl_access	6.013m	8.875ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	6.013m	8.875ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	13.618s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	11.994s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	15.968s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.971s		0	1	0.00
		chip_sw_aes_enc_jitter_en	43.970s	10.140us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	37.100s	10.200us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	44.810s	10.100us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	52.670s	10.400us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.043s		0	1	0.00
		chip_sw_clkmgr_jitter	3.672m	4.831ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	6.794m	6.884ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	6.794m	6.884ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	5.575m	5.436ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.769m	5.283ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.802m	3.738ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.204m	4.933ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	6.605m	5.356ms	0	1	0.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.429m	4.212ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.782m	5.495ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	26.808m	20.018ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	26.808m	20.018ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.722m	3.735ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.773m	5.431ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.428m	3.342ms	1	1	100.00
		chip_sw_csrng_smoketest	3.967m	4.520ms	1	1	100.00
		chip_sw_gpio_smoketest	3.654m	5.197ms	1	1	100.00
		chip_sw_hmac_smoketest	4.287m	4.565ms	1	1	100.00
		chip_sw_kmac_smoketest	3.944m	3.703ms	1	1	100.00
		chip_sw_otbn_smoketest	4.726m	5.362ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.349m	5.202ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.470m	3.497ms	1	1	100.00
		chip_sw_rv_timer_smoketest	5.169m	4.573ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.545m	4.876ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.754m	4.090ms	1	1	100.00
		chip_sw_uart_smoketest	3.568m	3.692ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.352s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	12.297s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.311m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	14.222s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	5.010m	5.990ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.014m	4.651ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.181m	4.420ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.671m	5.987ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	11.853s		0	1	0.00
		chip_rv_dm_lc_disabled	12.554m	16.015ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	12.419s		0	1	0.00
		chip_sw_lc_walkthrough_prod	12.514s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	12.355s		0	1	0.00
		chip_sw_lc_walkthrough_rma	11.949s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	11.853s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	13.994s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	13.185s		0	1	0.00
		rom_volatile_raw_unlock	12.673s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.456s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	55.456s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.285m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.906m	4.378ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.906m	4.378ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	9.090s		0	1	0.00
		chip_same_csr_outstanding	13.870s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	9.090s		0	1	0.00
		chip_same_csr_outstanding	13.870s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	1.635m	255.779us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.480s	11.871us	1	1	100.00
		xbar_smoke_large_delays	4.526m	2.338ms	1	1	100.00
		xbar_smoke_slow_rsp	5.365m	1.926ms	1	1	100.00
		xbar_random_zero_delays	11.580s	12.981us	1	1	100.00
		xbar_random_large_delays	13.786m	6.772ms	1	1	100.00
		xbar_random_slow_rsp	30.680m	11.613ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.871m	198.821us	1	1	100.00
		xbar_error_and_unmapped_addr	20.310s	17.513us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	7.530s	8.626us	1	1	100.00
		xbar_error_and_unmapped_addr	20.310s	17.513us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.015m	127.366us	1	1	100.00
		xbar_access_same_device_slow_rsp	13.192m	4.685ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	2.642m	413.790us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	20.182m	3.103ms	1	1	100.00
		xbar_stress_all_with_error	4.229m	206.588us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	10.401m	317.291us	1	1	100.00
		xbar_stress_all_with_reset_error	21.175m	1.644ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.582s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	13.793s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	11.910s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	14.714s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	13.806s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.529s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	15.730s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	12.506s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	15.931s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	14.002s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	12.609s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	13.712s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	12.957s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	49.591s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	58.647s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	49.954s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	54.480s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	49.847s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	46.620s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	44.394s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	38.097s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	48.288s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	39.530s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	38.087s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	24.590s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	31.502s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	29.998s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	29.776s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	18.101s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	14.823s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	13.187s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	15.052s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	16.861s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.581s		0	1	0.00
		rom_e2e_asm_init_dev	15.253s		0	1	0.00
		rom_e2e_asm_init_prod	12.265s		0	1	0.00
		rom_e2e_asm_init_prod_end	13.098s		0	1	0.00
		rom_e2e_asm_init_rma	12.421s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	12.750s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	13.001s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	12.185s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.784s		0	1	0.00
V2		TOTAL			64	205	31.22
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.581m	5.763ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.581m	4.873ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	12.919s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.676s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.884s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.683s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	20.725m	15.219ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	16.709s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	17.748m	13.189ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	12.612s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	16.136s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	12.919s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.676s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.884s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.789s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.762s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.530s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.811s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	24.550m	16.020ms	1	1	100.00
		chip_sw_entropy_src_kat_test	3.854m	3.588ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	4.073m	4.537ms	1	1	100.00
		chip_plic_all_irqs_0	9.851m	7.641ms	1	1	100.00
		chip_plic_all_irqs_10	10.873m	6.823ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.819m	5.105ms	1	1	100.00
		chip_sw_dma_abort	4.866m	4.688ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.329s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.796s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.297s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.584s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	12.685s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.475s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.764s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.164s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.940s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.767s		0	1	0.00
		chip_sw_entropy_src_smoketest	4.288m	3.723ms	1	1	100.00
		chip_sw_mbx_smoketest	5.169m	5.900ms	1	1	100.00
		TOTAL			78	250	31.20

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.45127941061809489050306505315517541715431579767175951672767369929104365983571
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 125.732s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.9928393428041355432238718993335510229563852922369736013722339528253377531114
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 115.600s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.22612271028921422678423754204338056398551493206960635175550473777988249549431
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 114.200s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.14072017728743393928969575394013776938274722767786098273906499721464013977279
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 100.672s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.101660414220289504231613575356729459564025931229786365378755601510492169766697
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Target //sw/device/tests:uart_tx_rx_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 88.271s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.41978814077253702744015395118464464407928334463079277646172335025080434581534
    Line 380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.24807841762381557641718192151592682380626435714641417589012470120097939979779
    Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.23212803256843244888854378587695321511230203262615777986736906102414343792912
    Line 378, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.34552994325750058655428868644389055320412609753915528399987824143652440329036
    Line 380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.41603932249769620049052041492800497522515730961512210321025223381773026601204
    Line 384, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.93269446328009402477123849479552137732819809190898509335511788292623912645113
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.114858118721640407779248173463338277702741484971817776072019540174935801309983
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.107862145745349529051073870259503952414921845317202072453965265367000449566942
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.5244273991916651086099028810207203110728274754508299302142942642188961102893
Line 419, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20018.489854 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20018.489854 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.90929514302064968756702900005290985926822024816676112856190722486599750233365
Line 384, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18018.670159 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.670159 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.113321697844183470776737417520351424948029616045500191994265952147600289027824
Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18027.015395 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18027.015395 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.41061046315124851154210446122011316240850646041685452828638466476925000113587
Line 399, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12018.485869 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.485869 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.27734061843657370123213526088852119926171027516819151947603524308659538699224
Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12026.832923 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.832923 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.27790790401076561184433392712237019050273646789625578160179041852409643162252
Line 399, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12026.742280 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.742280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.92850822617522170197742465031234846501056010608447550580897851493795852110487
Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 7173.100514 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (7760347949120270990200631336850889091762996082469633872240229118298578354443391196584105019842173266461758014164194797538990272818255702130014953123699804 [0x942bca66aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3127d7a977f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 7173.100514 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.105143826253289521904746274013958788787338936225505330096440350069515410547886
Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 5965.218335 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (8572826926098613813796403092214389353097658020376863625065475003661189359200865729044258441470961293111416526629871622099701341994058968840451022976801884 [0xa3af1aeaaae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd325f9aa1b7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 5965.218335 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.86969304489934520637318347343548278685003357788819670149566124476712996660528
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4949.300059 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: 'h30480000  a_data: 'h1bf9f7e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h26  a_opcode: 'h0  a_user: 'h26923  d_param: 'h0  d_source: 'h26  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4949.300059 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.111376219403771494192038160762193827883243110279331226158435900545401585260575
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 5426.501751 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: 'h30480000  a_data: 'h17fbe226  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h13  a_opcode: 'h1  a_user: 'h24881  d_param: 'h0  d_source: 'h13  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5426.501751 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.28547253493379315563846611973863262736902434958218926066349479417489577926876
    Line 1366, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.19495323158835953687577442765512286728916073084331170669311766713775045134245
    Line 423, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4701.180932 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4701.180932 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.1275014425612298177917338554756886374655951914973352593287482345817641015845
    Line 638, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 7845.978826 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 7845.978826 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.39738334093469359365775499706934390775630943129249710249087620701968882370166
    Line 383, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5436.015872 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5436.015872 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.94313073588479479425330773030407833836324240932286100939684611155816409840477
    Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 5283.360525 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 5283.360525 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.57016931298553099793137048097933105726218560173356477700369457531189362867138
    Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 3458.600852 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 3458.600852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == * has 1 failures:
- Test chip_sw_rv_core_ibex_rnd has 1 failures.
  - 0.chip_sw_rv_core_ibex_rnd.82181483598256184412013407521231637314549076047761562000582062430161884737328
    Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_rnd/latest/run.log
```
  UVM_ERROR @ 5355.777955 us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == 0
  UVM_INFO @ 5355.777955 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.32340078041710067976058402931179017685326223968519237492805901575988946104785
    Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 4933.349546 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 4933.349546 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.69391620277297475411395735107455488030028986338700943196634321461901646880471
    Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.103384410398826653022301763921363018056506342785223002744273598499095886731122
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 4377.933720 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 4377.933720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.88807563170548952309641765630759531761589666343207925656011482045249286165362
    Line 376, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 13959.499074 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 13959.499074 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.13341327251596394142292615694472782476018672634917371561951154752427167671631
    Line 256, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 16014.640246 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x40428 read out mismatch
  UVM_INFO @ 16014.640246 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.84407863593931599003537071653767264364473334916842823215159595187406392484559
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.10297442779255415115942894801671119950713341982744330451343113118658331555433
    Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 4688.150536 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4688.150536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```