DMA Simulation Results

Tuesday September 30 2025 16:05:14 UTC

GitHub Revision: 098ab72

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	5.000s	340.930us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	6.000s	295.061us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	4.000s	287.561us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	1.000s	46.503us	1	1	100.00
V1	csr_rw	dma_csr_rw	2.000s	33.398us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	6.000s	2.926ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	4.000s	4.412ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	33.798us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	2.000s	33.398us	1	1	100.00
		dma_csr_aliasing	4.000s	4.412ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	36.000s	2.431ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	6.433m	71.281ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	1.850m	35.160ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	1.850m	35.160ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	6.433m	71.281ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	5.183m	653.163ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	1.850m	35.160ms	1	1	100.00
V2	dma_abort	dma_abort	14.000s	4.268ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	2.383m	28.656ms	1	1	100.00
V2	alert_test	dma_alert_test	2.000s	25.129us	1	1	100.00
V2	intr_test	dma_intr_test	1.000s	16.624us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	2.000s	290.687us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	2.000s	290.687us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	1.000s	46.503us	1	1	100.00
		dma_csr_rw	2.000s	33.398us	1	1	100.00
		dma_csr_aliasing	4.000s	4.412ms	1	1	100.00
		dma_same_csr_outstanding	2.000s	43.916us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	1.000s	46.503us	1	1	100.00
		dma_csr_rw	2.000s	33.398us	1	1	100.00
		dma_csr_aliasing	4.000s	4.412ms	1	1	100.00
		dma_same_csr_outstanding	2.000s	43.916us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	11.000s	53.240us	1	1	100.00
		dma_generic_stress	5.183m	653.163ms	1	1	100.00
		dma_handshake_stress	1.850m	35.160ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	8.000s	1.308ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	2.000s	89.568us	1	1	100.00
		dma_sec_cm	1.000s	35.708us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	1.417m	10.405ms	1	1	100.00
		dma_longer_transfer	3.000s	111.962us	1	1	100.00
		dma_stress_all_with_rand_reset	6.000s	1.528ms	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.34457149261064717924190372487704123041458402947754151867224268164479734662905
      Line 104, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1527822186ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1527822186ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---