EDN Simulation Results

Tuesday September 30 2025 16:05:14 UTC

GitHub Revision: 098ab72

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.000s 25.533us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.890s 50.537us 1 1 100.00
V1 csr_rw edn_csr_rw 0.770s 29.064us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 2.380s 59.374us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.080s 20.598us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 0.960s 17.003us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.770s 29.064us 1 1 100.00
edn_csr_aliasing 1.080s 20.598us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.180s 220.434us 1 1 100.00
V2 csrng_commands edn_genbits 1.180s 220.434us 1 1 100.00
V2 genbits edn_genbits 1.180s 220.434us 1 1 100.00
V2 interrupts edn_intr 0.850s 24.172us 1 1 100.00
V2 alerts edn_alert 1.010s 129.992us 1 1 100.00
V2 errs edn_err 0.950s 19.690us 1 1 100.00
V2 disable edn_disable 0.760s 81.269us 1 1 100.00
edn_disable_auto_req_mode 0.920s 95.205us 1 1 100.00
V2 stress_all edn_stress_all 0.980s 33.249us 1 1 100.00
V2 intr_test edn_intr_test 0.760s 63.332us 1 1 100.00
V2 alert_test edn_alert_test 0.800s 54.440us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.560s 427.484us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.560s 427.484us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.890s 50.537us 1 1 100.00
edn_csr_rw 0.770s 29.064us 1 1 100.00
edn_csr_aliasing 1.080s 20.598us 1 1 100.00
edn_same_csr_outstanding 0.960s 20.092us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.890s 50.537us 1 1 100.00
edn_csr_rw 0.770s 29.064us 1 1 100.00
edn_csr_aliasing 1.080s 20.598us 1 1 100.00
edn_same_csr_outstanding 0.960s 20.092us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 6.150s 537.661us 1 1 100.00
edn_tl_intg_err 1.470s 217.402us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 0.990s 20.152us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.010s 129.992us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.150s 537.661us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.150s 537.661us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 6.150s 537.661us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.150s 537.661us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.010s 129.992us 1 1 100.00
edn_sec_cm 6.150s 537.661us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.010s 129.992us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 1.470s 217.402us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets