ENTROPY_SRC/RNG_16BITS Simulation Results

Tuesday September 30 2025 16:05:14 UTC

GitHub Revision: 098ab72

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 28.237us 1 1 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 2.000s 42.969us 1 1 100.00
V1 csr_rw entropy_src_csr_rw 2.000s 314.323us 1 1 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 7.000s 295.199us 1 1 100.00
V1 csr_aliasing entropy_src_csr_aliasing 4.000s 266.199us 1 1 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 3.000s 56.602us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 2.000s 314.323us 1 1 100.00
entropy_src_csr_aliasing 4.000s 266.199us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware entropy_src_smoke 4.000s 28.237us 1 1 100.00
entropy_src_rng 4.800m 12.033ms 1 1 100.00
entropy_src_fw_ov 46.000s 16.541ms 1 1 100.00
V2 firmware_mode entropy_src_fw_ov 46.000s 16.541ms 1 1 100.00
V2 rng_mode entropy_src_rng 4.800m 12.033ms 1 1 100.00
V2 rng_max_rate entropy_src_rng_max_rate 8.000m 14.046ms 1 1 100.00
V2 health_checks entropy_src_rng 4.800m 12.033ms 1 1 100.00
V2 conditioning entropy_src_rng 4.800m 12.033ms 1 1 100.00
V2 interrupts entropy_src_rng 4.800m 12.033ms 1 1 100.00
entropy_src_intr 24.000s 11.987ms 1 1 100.00
V2 alerts entropy_src_rng 4.800m 12.033ms 1 1 100.00
entropy_src_functional_alerts 6.000s 354.784us 1 1 100.00
V2 stress_all entropy_src_stress_all 7.567m 20.327ms 1 1 100.00
V2 functional_errors entropy_src_functional_errors 2.000s 201.905us 1 1 100.00
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 4.000s 185.327us 1 1 100.00
V2 intr_test entropy_src_intr_test 2.000s 96.827us 1 1 100.00
V2 alert_test entropy_src_alert_test 2.000s 58.119us 1 1 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 5.000s 253.892us 1 1 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 5.000s 253.892us 1 1 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 2.000s 42.969us 1 1 100.00
entropy_src_csr_rw 2.000s 314.323us 1 1 100.00
entropy_src_csr_aliasing 4.000s 266.199us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 265.612us 1 1 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 2.000s 42.969us 1 1 100.00
entropy_src_csr_rw 2.000s 314.323us 1 1 100.00
entropy_src_csr_aliasing 4.000s 266.199us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 265.612us 1 1 100.00
V2 TOTAL 12 12 100.00
V2S tl_intg_err entropy_src_sec_cm 3.000s 164.003us 1 1 100.00
entropy_src_tl_intg_err 3.000s 597.284us 1 1 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.800m 12.033ms 1 1 100.00
entropy_src_cfg_regwen 2.000s 52.287us 1 1 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.800m 12.033ms 1 1 100.00
V2S sec_cm_config_redun entropy_src_rng 4.800m 12.033ms 1 1 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 4.800m 12.033ms 1 1 100.00
entropy_src_fw_ov 46.000s 16.541ms 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 2.000s 201.905us 1 1 100.00
entropy_src_sec_cm 3.000s 164.003us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 2.000s 201.905us 1 1 100.00
entropy_src_sec_cm 3.000s 164.003us 1 1 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.800m 12.033ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 2.000s 201.905us 1 1 100.00
entropy_src_sec_cm 3.000s 164.003us 1 1 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 2.000s 201.905us 1 1 100.00
entropy_src_sec_cm 3.000s 164.003us 1 1 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 2.000s 201.905us 1 1 100.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 6.000s 354.784us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 3.000s 597.284us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 1.383m 15.149ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 22 22 100.00