HMAC Simulation Results

Tuesday September 30 2025 16:05:14 UTC

GitHub Revision: 098ab72

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 3.630s 289.086us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.890s 67.670us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.790s 69.056us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.120s 375.948us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 2.150s 60.977us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 18.166m 104.750ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.790s 69.056us 1 1 100.00
hmac_csr_aliasing 2.150s 60.977us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 9.640s 1.302ms 1 1 100.00
V2 back_pressure hmac_back_pressure 15.490s 4.812ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.237m 6.274ms 1 1 100.00
hmac_test_sha384_vectors 18.370s 218.814us 1 1 100.00
hmac_test_sha512_vectors 6.770m 60.820ms 1 1 100.00
hmac_test_hmac256_vectors 5.950s 786.189us 1 1 100.00
hmac_test_hmac384_vectors 7.230s 274.664us 1 1 100.00
hmac_test_hmac512_vectors 8.660s 2.553ms 1 1 100.00
V2 burst_wr hmac_burst_wr 3.940s 1.166ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 6.265m 4.222ms 1 1 100.00
V2 error hmac_error 23.850s 3.141ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 34.970s 1.296ms 1 1 100.00
V2 save_and_restore hmac_smoke 3.630s 289.086us 1 1 100.00
hmac_long_msg 9.640s 1.302ms 1 1 100.00
hmac_back_pressure 15.490s 4.812ms 1 1 100.00
hmac_datapath_stress 6.265m 4.222ms 1 1 100.00
hmac_burst_wr 3.940s 1.166ms 1 1 100.00
hmac_stress_all 34.092m 314.618ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 3.630s 289.086us 1 1 100.00
hmac_long_msg 9.640s 1.302ms 1 1 100.00
hmac_back_pressure 15.490s 4.812ms 1 1 100.00
hmac_datapath_stress 6.265m 4.222ms 1 1 100.00
hmac_wipe_secret 34.970s 1.296ms 1 1 100.00
hmac_test_sha256_vectors 3.237m 6.274ms 1 1 100.00
hmac_test_sha384_vectors 18.370s 218.814us 1 1 100.00
hmac_test_sha512_vectors 6.770m 60.820ms 1 1 100.00
hmac_test_hmac256_vectors 5.950s 786.189us 1 1 100.00
hmac_test_hmac384_vectors 7.230s 274.664us 1 1 100.00
hmac_test_hmac512_vectors 8.660s 2.553ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 3.630s 289.086us 1 1 100.00
hmac_long_msg 9.640s 1.302ms 1 1 100.00
hmac_back_pressure 15.490s 4.812ms 1 1 100.00
hmac_datapath_stress 6.265m 4.222ms 1 1 100.00
hmac_burst_wr 3.940s 1.166ms 1 1 100.00
hmac_error 23.850s 3.141ms 1 1 100.00
hmac_wipe_secret 34.970s 1.296ms 1 1 100.00
hmac_test_sha256_vectors 3.237m 6.274ms 1 1 100.00
hmac_test_sha384_vectors 18.370s 218.814us 1 1 100.00
hmac_test_sha512_vectors 6.770m 60.820ms 1 1 100.00
hmac_test_hmac256_vectors 5.950s 786.189us 1 1 100.00
hmac_test_hmac384_vectors 7.230s 274.664us 1 1 100.00
hmac_test_hmac512_vectors 8.660s 2.553ms 1 1 100.00
hmac_stress_all 34.092m 314.618ms 1 1 100.00
V2 stress_all hmac_stress_all 34.092m 314.618ms 1 1 100.00
V2 alert_test hmac_alert_test 0.690s 12.436us 1 1 100.00
V2 intr_test hmac_intr_test 0.580s 14.426us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.060s 2.811ms 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.060s 2.811ms 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.890s 67.670us 1 1 100.00
hmac_csr_rw 0.790s 69.056us 1 1 100.00
hmac_csr_aliasing 2.150s 60.977us 1 1 100.00
hmac_same_csr_outstanding 1.400s 129.946us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.890s 67.670us 1 1 100.00
hmac_csr_rw 0.790s 69.056us 1 1 100.00
hmac_csr_aliasing 2.150s 60.977us 1 1 100.00
hmac_same_csr_outstanding 1.400s 129.946us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.890s 422.371us 1 1 100.00
hmac_tl_intg_err 2.140s 165.693us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.140s 165.693us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 3.630s 289.086us 1 1 100.00
V3 stress_reset hmac_stress_reset 2.240s 263.382us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 44.160s 12.569ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 3.060s 63.612us 1 1 100.00
TOTAL 28 28 100.00