I2C Simulation Results

Tuesday September 30 2025 16:05:14 UTC

GitHub Revision: 098ab72

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	49.910s	1.567ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	13.230s	2.628ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.760s	206.251us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.770s	29.201us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.680s	1.504ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.130s	536.177us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.310s	91.244us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.770s	29.201us	1	1	100.00
		i2c_csr_aliasing	1.130s	536.177us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.840s	61.817us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	0.930s	51.486us	0	1	0.00
V2	host_maxperf	i2c_host_perf	1.456m	12.113ms	1	1	100.00
V2	host_override	i2c_host_override	0.700s	30.127us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	59.830s	8.087ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	40.960s	11.291ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.850s	130.644us	1	1	100.00
		i2c_host_fifo_fmt_empty	3.520s	257.616us	1	1	100.00
		i2c_host_fifo_reset_rx	6.080s	315.096us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.286m	2.277ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	31.020s	3.693ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.100s	130.919us	1	1	100.00
V2	target_glitch	i2c_target_glitch	1.930s	636.518us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	53.420s	68.029ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.870s	3.430ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	41.780s	1.315ms	1	1	100.00
		i2c_target_intr_smoke	3.000s	729.385us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.440s	734.752us	1	1	100.00
		i2c_target_fifo_reset_tx	1.590s	210.995us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	29.440s	19.475ms	1	1	100.00
		i2c_target_stress_rd	41.780s	1.315ms	1	1	100.00
		i2c_target_intr_stress_wr	35.840s	15.137ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	6.970s	1.382ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	15.460s	2.061ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.310s	3.240ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	20.570s	10.180ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.310s	2.010ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.890s	621.367us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	1.456m	12.113ms	1	1	100.00
		i2c_host_perf_precise	1.360s	109.531us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	31.020s	3.693ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	4.240s	449.233us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.060s	943.903us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.200s	511.684us	1	1	100.00
		i2c_target_nack_txstretch	1.220s	534.558us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	12.010s	429.696us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.170s	1.788ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.610s	43.565us	1	1	100.00
V2	intr_test	i2c_intr_test	0.820s	44.204us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.550s	54.411us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.550s	54.411us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.760s	206.251us	1	1	100.00
		i2c_csr_rw	0.770s	29.201us	1	1	100.00
		i2c_csr_aliasing	1.130s	536.177us	1	1	100.00
		i2c_same_csr_outstanding	0.920s	83.086us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.760s	206.251us	1	1	100.00
		i2c_csr_rw	0.770s	29.201us	1	1	100.00
		i2c_csr_aliasing	1.130s	536.177us	1	1	100.00
		i2c_same_csr_outstanding	0.920s	83.086us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	1.970s	463.486us	1	1	100.00
		i2c_sec_cm	0.830s	44.977us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.970s	463.486us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	15.070s	17.974ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.150s	80.363us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	11.190s	1.707ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.10682742465297715133005288652501687397419382107242363022115657541983697332592
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  61817479 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  61817479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.70138714865826829776295134073732693295167541660547840199963991359188620118607
      Line 89, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @  51486144 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  51486144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.78070118053698244647243112828899623414653870937812024913057146828213483153169
      Line 86, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17973601714 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 17973601714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.57332234291493978838803574198339806127691104173751006968992660538521822793562
      Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1706609213 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1706609213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.77717682673020150701478205951414462095776097102568004082753244310137921541767
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 636517561 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 636517561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.89423600272139350414752523566321546756268160688819384375547565703598322265072
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @  80362987 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 106 [0x6a])
        UVM_INFO @  80362987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.73640610841689652949887473851299669558200946186098957454326452820872585184827
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10180047739 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10180047739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---