KEYMGR Simulation Results

Tuesday September 30 2025 16:05:14 UTC

GitHub Revision: 098ab72

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 2.410s 935.407us 1 1 100.00
V1 random keymgr_random 2.760s 72.590us 1 1 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 0.780s 19.606us 1 1 100.00
V1 csr_rw keymgr_csr_rw 0.800s 41.863us 1 1 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 5.180s 255.343us 1 1 100.00
V1 csr_aliasing keymgr_csr_aliasing 3.180s 186.764us 1 1 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.800s 58.983us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 0.800s 41.863us 1 1 100.00
keymgr_csr_aliasing 3.180s 186.764us 1 1 100.00
V1 TOTAL 7 7 100.00
V2 cfgen_during_op keymgr_cfg_regwen 5.770s 164.778us 1 1 100.00
V2 sideload keymgr_sideload 2.880s 811.014us 1 1 100.00
keymgr_sideload_kmac 2.880s 187.078us 1 1 100.00
keymgr_sideload_aes 3.800s 734.843us 1 1 100.00
keymgr_sideload_otbn 1.770s 83.480us 1 1 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 1.780s 168.137us 1 1 100.00
V2 lc_disable keymgr_lc_disable 2.650s 172.187us 1 1 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 1.950s 44.076us 1 1 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 6.160s 299.100us 1 1 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 2.730s 360.138us 1 1 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 1.630s 29.389us 1 1 100.00
V2 stress_all keymgr_stress_all 1.187m 3.628ms 1 1 100.00
V2 intr_test keymgr_intr_test 0.690s 17.225us 1 1 100.00
V2 alert_test keymgr_alert_test 0.720s 15.865us 1 1 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 1.450s 79.590us 1 1 100.00
V2 tl_d_illegal_access keymgr_tl_errors 1.450s 79.590us 1 1 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 0.780s 19.606us 1 1 100.00
keymgr_csr_rw 0.800s 41.863us 1 1 100.00
keymgr_csr_aliasing 3.180s 186.764us 1 1 100.00
keymgr_same_csr_outstanding 1.710s 38.105us 1 1 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 0.780s 19.606us 1 1 100.00
keymgr_csr_rw 0.800s 41.863us 1 1 100.00
keymgr_csr_aliasing 3.180s 186.764us 1 1 100.00
keymgr_same_csr_outstanding 1.710s 38.105us 1 1 100.00
V2 TOTAL 16 16 100.00
V2S sec_cm_additional_check keymgr_sec_cm 17.730s 4.493ms 1 1 100.00
V2S tl_intg_err keymgr_sec_cm 17.730s 4.493ms 1 1 100.00
keymgr_tl_intg_err 2.620s 417.340us 1 1 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 1.780s 526.540us 1 1 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 1.780s 526.540us 1 1 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 1.780s 526.540us 1 1 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 1.780s 526.540us 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 14.690s 6.049ms 1 1 100.00
V2S prim_count_check keymgr_sec_cm 17.730s 4.493ms 1 1 100.00
V2S prim_fsm_check keymgr_sec_cm 17.730s 4.493ms 1 1 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 2.620s 417.340us 1 1 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 1.780s 526.540us 1 1 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 5.770s 164.778us 1 1 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 2.760s 72.590us 1 1 100.00
keymgr_csr_rw 0.800s 41.863us 1 1 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 2.760s 72.590us 1 1 100.00
keymgr_csr_rw 0.800s 41.863us 1 1 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 2.760s 72.590us 1 1 100.00
keymgr_csr_rw 0.800s 41.863us 1 1 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 2.650s 172.187us 1 1 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 2.730s 360.138us 1 1 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 2.730s 360.138us 1 1 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 2.760s 72.590us 1 1 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 3.400s 553.061us 1 1 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 17.730s 4.493ms 1 1 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 17.730s 4.493ms 1 1 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 17.730s 4.493ms 1 1 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 2.370s 90.097us 1 1 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 2.650s 172.187us 1 1 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 17.730s 4.493ms 1 1 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 17.730s 4.493ms 1 1 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 17.730s 4.493ms 1 1 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 2.370s 90.097us 1 1 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 2.370s 90.097us 1 1 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 17.730s 4.493ms 1 1 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 2.370s 90.097us 1 1 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 17.730s 4.493ms 1 1 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 2.370s 90.097us 1 1 100.00
V2S TOTAL 6 6 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 7.800s 413.292us 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 30 100.00