098ab72| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 52.000s | 5.853ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 5.000s | 17.427us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 5.000s | 31.446us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 2.000s | 127.995us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 2.000s | 78.826us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 2.000s | 43.722us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 5.000s | 31.446us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 2.000s | 78.826us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | mbx_stress | mbx_stress | 25.000s | 7.908ms | 0 | 1 | 0.00 |
| V2 | mbx_max_activity | mbx_stress_zero_delays | 39.000s | 2.216ms | 1 | 1 | 100.00 |
| V2 | mbx_imbx_oob | mbx_imbx_oob | 1.017m | 6.197ms | 1 | 1 | 100.00 |
| V2 | mbx_doe_intr_msg | mbx_doe_intr_msg | 18.000s | 2.147ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 2.000s | 110.781us | 1 | 1 | 100.00 |
| V2 | intr_test | mbx_intr_test | 7.000s | 32.894us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 12.000s | 44.485us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 12.000s | 44.485us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 5.000s | 17.427us | 1 | 1 | 100.00 |
| mbx_csr_rw | 5.000s | 31.446us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 2.000s | 78.826us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 2.000s | 44.478us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 5.000s | 17.427us | 1 | 1 | 100.00 |
| mbx_csr_rw | 5.000s | 31.446us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 2.000s | 78.826us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 2.000s | 44.478us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 7 | 8 | 87.50 | |||
| V2S | tl_intg_err | mbx_tl_intg_err | 11.000s | 411.862us | 1 | 1 | 100.00 |
| mbx_sec_cm | 1.000s | 13.038us | 1 | 1 | 100.00 | ||
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| TOTAL | 15 | 16 | 93.75 |
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 1 failures:
0.mbx_stress.7821967771613196328796963045663571432846755554465823417872379940659404450495
Line 554, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest/run.log
UVM_ERROR @ 7908291823 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 7908291823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---