OTBN Simulation Results

Tuesday September 30 2025 16:05:14 UTC

GitHub Revision: 098ab72

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 8.000s 275.688us 0 1 0.00
V1 single_binary otbn_single 5.000s 13.716us 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 4.000s 42.070us 1 1 100.00
V1 csr_rw otbn_csr_rw 3.000s 122.488us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 5.000s 64.955us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 4.000s 25.952us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 4.000s 136.801us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 3.000s 122.488us 1 1 100.00
otbn_csr_aliasing 4.000s 25.952us 1 1 100.00
V1 mem_walk otbn_mem_walk 36.000s 1.910ms 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 8.000s 136.545us 1 1 100.00
V1 TOTAL 7 9 77.78
V2 reset_recovery otbn_reset 18.000s 66.665us 0 1 0.00
V2 multi_error otbn_multi_err 39.000s 715.338us 0 1 0.00
V2 back_to_back otbn_multi 36.000s 308.145us 0 1 0.00
V2 stress_all otbn_stress_all 18.000s 64.974us 0 1 0.00
V2 lc_escalation otbn_escalate 7.000s 63.071us 0 1 0.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 4.000s 40.430us 1 1 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 7.000s 60.452us 0 1 0.00
V2 alert_test otbn_alert_test 4.000s 21.166us 1 1 100.00
V2 intr_test otbn_intr_test 3.000s 15.367us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 4.000s 180.395us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 4.000s 180.395us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 4.000s 42.070us 1 1 100.00
otbn_csr_rw 3.000s 122.488us 1 1 100.00
otbn_csr_aliasing 4.000s 25.952us 1 1 100.00
otbn_same_csr_outstanding 5.000s 23.221us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 4.000s 42.070us 1 1 100.00
otbn_csr_rw 3.000s 122.488us 1 1 100.00
otbn_csr_aliasing 4.000s 25.952us 1 1 100.00
otbn_same_csr_outstanding 5.000s 23.221us 1 1 100.00
V2 TOTAL 5 11 45.45
V2S mem_integrity otbn_imem_err 8.000s 70.018us 0 1 0.00
otbn_dmem_err 17.000s 84.619us 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 6.000s 188.206us 0 1 0.00
otbn_controller_ispr_rdata_err 7.000s 215.164us 0 1 0.00
otbn_mac_bignum_acc_err 7.000s 59.171us 0 1 0.00
otbn_urnd_err 9.000s 45.863us 1 1 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 4.000s 16.834us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 5.000s 127.203us 1 1 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 5.000s 49.335us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 6.850m 2.482ms 1 1 100.00
otbn_tl_intg_err 14.000s 681.190us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 5.000s 37.678us 0 1 0.00
V2S prim_fsm_check otbn_sec_cm 6.850m 2.482ms 1 1 100.00
V2S prim_count_check otbn_sec_cm 6.850m 2.482ms 1 1 100.00
V2S sec_cm_mem_scramble otbn_smoke 8.000s 275.688us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 17.000s 84.619us 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 8.000s 70.018us 0 1 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 14.000s 681.190us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 7.000s 63.071us 0 1 0.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 8.000s 70.018us 0 1 0.00
otbn_dmem_err 17.000s 84.619us 0 1 0.00
otbn_zero_state_err_urnd 4.000s 40.430us 1 1 100.00
otbn_illegal_mem_acc 4.000s 16.834us 1 1 100.00
otbn_sec_cm 6.850m 2.482ms 1 1 100.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 6.850m 2.482ms 1 1 100.00
V2S sec_cm_scramble_key_sideload otbn_single 5.000s 13.716us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 8.000s 70.018us 0 1 0.00
otbn_dmem_err 17.000s 84.619us 0 1 0.00
otbn_zero_state_err_urnd 4.000s 40.430us 1 1 100.00
otbn_illegal_mem_acc 4.000s 16.834us 1 1 100.00
otbn_sec_cm 6.850m 2.482ms 1 1 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 6.850m 2.482ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 7.000s 63.071us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 8.000s 70.018us 0 1 0.00
otbn_dmem_err 17.000s 84.619us 0 1 0.00
otbn_zero_state_err_urnd 4.000s 40.430us 1 1 100.00
otbn_illegal_mem_acc 4.000s 16.834us 1 1 100.00
otbn_sec_cm 6.850m 2.482ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 6.850m 2.482ms 1 1 100.00
V2S sec_cm_data_reg_sw_sca otbn_single 5.000s 13.716us 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 5.000s 13.577us 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 5.000s 21.877us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 24.000s 92.041us 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 24.000s 92.041us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 7.000s 18.720us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 6.850m 2.482ms 1 1 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 6.850m 2.482ms 1 1 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 7.000s 216.533us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 6.850m 2.482ms 1 1 100.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 6.850m 2.482ms 1 1 100.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 7.000s 83.993us 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 7.000s 83.993us 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 5.000s 16.700us 1 1 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 5.000s 13.716us 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 5.000s 13.716us 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 5.000s 13.716us 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 36.000s 308.145us 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 5.000s 13.716us 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 5.000s 13.716us 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 12.000s 233.995us 0 1 0.00
V2S sec_cm_key_sideload otbn_single 5.000s 13.716us 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 6.850m 2.482ms 1 1 100.00
V2S TOTAL 8 20 40.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 4.317m 4.026ms 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 41 48.78

Failure Buckets