RV_TIMER Simulation Results

Tuesday September 30 2025 16:05:14 UTC

GitHub Revision: 098ab72

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.720s	39.572us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.670s	46.571us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.710s	145.199us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.000s	61.643us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.810s	20.405us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.850s	227.823us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.710s	145.199us	1	1	100.00
		rv_timer_csr_aliasing	0.810s	20.405us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.750s	500.011us	0	1	0.00
V2	disabled	rv_timer_disabled	1.400s	897.114us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	7.183m	1.371s	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	7.183m	1.371s	1	1	100.00
V2	stress	rv_timer_stress_all	1.590s	792.363us	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.690s	84.660us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.750s	46.766us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.520s	229.779us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.520s	229.779us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.670s	46.571us	1	1	100.00
		rv_timer_csr_rw	0.710s	145.199us	1	1	100.00
		rv_timer_csr_aliasing	0.810s	20.405us	1	1	100.00
		rv_timer_same_csr_outstanding	0.980s	38.191us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.670s	46.571us	1	1	100.00
		rv_timer_csr_rw	0.710s	145.199us	1	1	100.00
		rv_timer_csr_aliasing	0.810s	20.405us	1	1	100.00
		rv_timer_same_csr_outstanding	0.980s	38.191us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	1.210s	420.841us	1	1	100.00
		rv_timer_tl_intg_err	1.200s	166.466us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.200s	166.466us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.670s	444.215us	0	1	0.00
V3	max_value	rv_timer_max	0.700s	45.999us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	13.510s	2.252ms	1	1	100.00
V3		TOTAL			1	3	33.33
		TOTAL			16	19	84.21

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.18673724324391167862302096665611722435190707757415604500828388946865936841596
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @ 444215088 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x5f65f904) == 0x1
        UVM_INFO @ 444215088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.50575513886213760817565456273356478457303681279809768084546865235204331606014
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 500010726 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xf369c104) == 0x1
        UVM_INFO @ 500010726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.60065814603963266196968629827482090734201244040232044430489825553584286293739
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @  45999350 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @  45999350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---