SPI_DEVICE/1R1W Simulation Results

Tuesday September 30 2025 16:05:14 UTC

GitHub Revision: 098ab72

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	2.184m	25.411ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.480s	110.736us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.990s	70.406us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.600s	1.888ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.920s	888.471us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.270s	149.383us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.990s	70.406us	1	1	100.00
		spi_device_csr_aliasing	11.920s	888.471us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.950s	14.080us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.600s	28.593us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.200s	19.312us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.000s	1.600us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.810s	3.719us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.020s	10.244us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.020s	10.244us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	12.390s	6.068ms	1	1	100.00
		spi_device_tpm_sts_read	0.970s	40.565us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	17.590s	1.424ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.830s	878.099us	1	1	100.00
		spi_device_flash_all	43.270s	10.085ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	25.480s	13.228ms	1	1	100.00
		spi_device_flash_all	43.270s	10.085ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	25.480s	13.228ms	1	1	100.00
		spi_device_flash_all	43.270s	10.085ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	43.270s	10.085ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.620s	1.608ms	1	1	100.00
		spi_device_flash_all	43.270s	10.085ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.620s	1.608ms	1	1	100.00
		spi_device_flash_all	43.270s	10.085ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.620s	1.608ms	1	1	100.00
		spi_device_flash_all	43.270s	10.085ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.620s	1.608ms	1	1	100.00
		spi_device_flash_all	43.270s	10.085ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.620s	1.608ms	1	1	100.00
		spi_device_flash_all	43.270s	10.085ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	6.710s	1.088ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	6.810s	436.706us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	6.810s	436.706us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	6.810s	436.706us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	7.380s	1.313ms	1	1	100.00
		spi_device_read_buffer_direct	13.780s	3.086ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	6.810s	436.706us	1	1	100.00
		spi_device_flash_all	43.270s	10.085ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	43.270s	10.085ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	43.270s	10.085ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.130s	392.282us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.130s	392.282us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	2.184m	25.411ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	2.139m	43.640ms	1	1	100.00
V2	stress_all	spi_device_stress_all	47.960s	15.288ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.910s	11.519us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.040s	16.204us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.860s	108.027us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.860s	108.027us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.480s	110.736us	1	1	100.00
		spi_device_csr_rw	1.990s	70.406us	1	1	100.00
		spi_device_csr_aliasing	11.920s	888.471us	1	1	100.00
		spi_device_same_csr_outstanding	1.610s	132.312us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.480s	110.736us	1	1	100.00
		spi_device_csr_rw	1.990s	70.406us	1	1	100.00
		spi_device_csr_aliasing	11.920s	888.471us	1	1	100.00
		spi_device_same_csr_outstanding	1.610s	132.312us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.250s	368.277us	1	1	100.00
		spi_device_tl_intg_err	5.140s	114.068us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	5.140s	114.068us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	14.380s	6.905ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.99346486474413610429029621417930659862337537043998166730492687206155151338115
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1089993 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[82])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1089993 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1089993 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[978])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.24301303890540848458213400038030684902471101410214175485233290640533754521532
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1049978 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x24b84f [1001001011100001001111] vs 0x0 [0])
        UVM_ERROR @   1085978 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6be85f [11010111110100001011111] vs 0x0 [0])
        UVM_ERROR @   1165978 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x124ab0 [100100100101010110000] vs 0x0 [0])
        UVM_ERROR @   1233978 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8ec11 [10001110110000010001] vs 0x0 [0])
        UVM_ERROR @   1309978 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xaf655f [101011110110010101011111] vs 0x0 [0])