SPI_HOST Simulation Results

Tuesday September 30 2025 16:05:14 UTC

GitHub Revision: 098ab72

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	25.000s	2.497ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	1.000s	58.901us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	1.000s	15.856us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	3.000s	335.685us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	51.178us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	27.763us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.000s	15.856us	1	1	100.00
		spi_host_csr_aliasing	2.000s	51.178us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	119.636us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	18.531us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	1.000s	23.689us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.000s	171.369us	1	1	100.00
		spi_host_error_cmd	1.000s	27.063us	1	1	100.00
		spi_host_event	10.000s	1.246ms	1	1	100.00
V2	clock_rate	spi_host_speed	2.000s	166.001us	1	1	100.00
V2	speed	spi_host_speed	2.000s	166.001us	1	1	100.00
V2	chip_select_timing	spi_host_speed	2.000s	166.001us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	3.000s	165.329us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	1.000s	24.835us	1	1	100.00
V2	cpol_cpha	spi_host_speed	2.000s	166.001us	1	1	100.00
V2	full_cycle	spi_host_speed	2.000s	166.001us	1	1	100.00
V2	duplex	spi_host_smoke	25.000s	2.497ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	25.000s	2.497ms	1	1	100.00
V2	stress_all	spi_host_stress_all	4.000s	141.516us	1	1	100.00
V2	spien	spi_host_spien	8.000s	468.578us	1	1	100.00
V2	stall	spi_host_status_stall	54.000s	1.761ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	3.000s	89.817us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	2.000s	171.369us	1	1	100.00
V2	alert_test	spi_host_alert_test	2.000s	21.808us	1	1	100.00
V2	intr_test	spi_host_intr_test	1.000s	30.963us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	41.060us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	41.060us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	1.000s	58.901us	1	1	100.00
		spi_host_csr_rw	1.000s	15.856us	1	1	100.00
		spi_host_csr_aliasing	2.000s	51.178us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	51.622us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	1.000s	58.901us	1	1	100.00
		spi_host_csr_rw	1.000s	15.856us	1	1	100.00
		spi_host_csr_aliasing	2.000s	51.178us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	51.622us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	87.199us	1	1	100.00
		spi_host_sec_cm	1.000s	292.070us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	87.199us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	7.333m	30.320ms	1	1	100.00
		TOTAL			26	26	100.00