SRAM_CTRL/MAIN Simulation Results

Tuesday September 30 2025 16:05:14 UTC

GitHub Revision: 098ab72

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	4.880s	771.435us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.830s	20.936us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.650s	40.060us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.810s	336.123us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.690s	41.530us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.060s	732.105us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.650s	40.060us	1	1	100.00
		sram_ctrl_csr_aliasing	0.690s	41.530us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.780m	14.563ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	50.050s	2.278ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	12.451m	41.494ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.990m	3.998ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	13.166m	134.133ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.223m	60.476ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	13.550s	12.686ms	1	1	100.00
V2	executable	sram_ctrl_executable	8.019m	74.709ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	2.860s	1.538ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.572m	22.134ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	32.900s	5.632ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	55.470s	785.381us	1	1	100.00
		sram_ctrl_throughput_w_readback	6.210s	753.255us	1	1	100.00
V2	regwen	sram_ctrl_regwen	2.887m	49.106ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.830s	358.823us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	15.337m	107.174ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.790s	20.441us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.170s	296.344us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.170s	296.344us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.830s	20.936us	1	1	100.00
		sram_ctrl_csr_rw	0.650s	40.060us	1	1	100.00
		sram_ctrl_csr_aliasing	0.690s	41.530us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.840s	39.055us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.830s	20.936us	1	1	100.00
		sram_ctrl_csr_rw	0.650s	40.060us	1	1	100.00
		sram_ctrl_csr_aliasing	0.690s	41.530us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.840s	39.055us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	36.190s	21.384ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.820s	4.413us	0	1	0.00
		sram_ctrl_tl_intg_err	2.780s	683.515us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.820s	4.413us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.780s	683.515us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	2.887m	49.106ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	2.887m	49.106ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.650s	40.060us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	8.019m	74.709ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	8.019m	74.709ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	8.019m	74.709ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	13.550s	12.686ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.000s	2.769ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	36.190s	21.384ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	6.970s	1.381ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	4.880s	771.435us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	4.880s	771.435us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	8.019m	74.709ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.820s	4.413us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	13.550s	12.686ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.820s	4.413us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.820s	4.413us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	4.880s	771.435us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.820s	4.413us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	25.450s	1.438ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(depth_o <= *'(Depth))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.111845093031329663728412431429559153113740106479338866131344039683260441849476
      Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   4412664 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   4412664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---