SRAM_CTRL/RET Simulation Results

Tuesday September 30 2025 16:05:14 UTC

GitHub Revision: 098ab72

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	10.110s	618.337us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.830s	105.271us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.800s	37.051us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.930s	697.777us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.980s	41.023us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.250s	105.479us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.800s	37.051us	1	1	100.00
		sram_ctrl_csr_aliasing	0.980s	41.023us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.030s	140.257us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.470s	63.111us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	multiple_keys	sram_ctrl_multiple_keys	1.184m	13.178ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.979m	8.666ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	51.390s	3.320ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	8.140m	11.222ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.500s	533.270us	1	1	100.00
V2	executable	sram_ctrl_executable	5.204m	8.499ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	6.840s	2.917ms	1	1	100.00
		sram_ctrl_partial_access_b2b	1.768m	4.437ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	5.890s	253.287us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	1.080s	43.443us	1	1	100.00
		sram_ctrl_throughput_w_readback	42.090s	406.493us	1	1	100.00
V2	regwen	sram_ctrl_regwen	14.900m	3.443ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.790s	28.644us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	1.662m	14.834ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.680s	40.861us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.550s	108.115us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.550s	108.115us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.830s	105.271us	1	1	100.00
		sram_ctrl_csr_rw	0.800s	37.051us	1	1	100.00
		sram_ctrl_csr_aliasing	0.980s	41.023us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.070s	26.881us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.830s	105.271us	1	1	100.00
		sram_ctrl_csr_rw	0.800s	37.051us	1	1	100.00
		sram_ctrl_csr_aliasing	0.980s	41.023us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.070s	26.881us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.670s	448.500us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.780s	26.575us	0	1	0.00
		sram_ctrl_tl_intg_err	1.550s	489.078us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.780s	26.575us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.550s	489.078us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	14.900m	3.443ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	14.900m	3.443ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.800s	37.051us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.204m	8.499ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.204m	8.499ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.204m	8.499ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.500s	533.270us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.150s	49.570us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.670s	448.500us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.960s	36.040us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	10.110s	618.337us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	10.110s	618.337us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.204m	8.499ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.780s	26.575us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.500s	533.270us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.780s	26.575us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.780s	26.575us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	10.110s	618.337us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.780s	26.575us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	54.170s	2.711ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.103535999027379543453947781651448589792103357477018452110245310816172968275441
      Line 102, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  26575484 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  26575484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.sram_ctrl_csr_mem_rw_with_rand_reset.60849645464004765815752832254560784391281019536866724071615502846603527512748
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 105479041 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (5 [0x5] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
        UVM_INFO @ 105479041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---