UART Simulation Results

Tuesday September 30 2025 16:05:14 UTC

GitHub Revision: 098ab72

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.180s	662.420us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.990s	1.095ms	1	1	100.00
V1	csr_rw	uart_csr_rw	0.640s	13.485us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.850s	1.149ms	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.770s	27.026us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.810s	41.874us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.640s	13.485us	1	1	100.00
		uart_csr_aliasing	0.770s	27.026us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	4.170s	5.626ms	1	1	100.00
V2	parity	uart_smoke	2.180s	662.420us	1	1	100.00
		uart_tx_rx	4.170s	5.626ms	1	1	100.00
V2	parity_error	uart_intr	29.480s	29.351ms	1	1	100.00
		uart_rx_parity_err	2.547m	215.042ms	1	1	100.00
V2	watermark	uart_tx_rx	4.170s	5.626ms	1	1	100.00
		uart_intr	29.480s	29.351ms	1	1	100.00
V2	fifo_full	uart_fifo_full	45.940s	264.495ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.964m	89.533ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	20.630s	266.004ms	1	1	100.00
V2	rx_frame_err	uart_intr	29.480s	29.351ms	1	1	100.00
V2	rx_break_err	uart_intr	29.480s	29.351ms	1	1	100.00
V2	rx_timeout	uart_intr	29.480s	29.351ms	1	1	100.00
V2	perf	uart_perf	4.636m	15.656ms	1	1	100.00
V2	sys_loopback	uart_loopback	8.080s	11.466ms	1	1	100.00
V2	line_loopback	uart_loopback	8.080s	11.466ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.100s	1.189ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.120s	1.972ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	6.630s	7.991ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	4.980s	3.374ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	6.826m	102.276ms	1	1	100.00
V2	stress_all	uart_stress_all	3.680m	160.687ms	1	1	100.00
V2	alert_test	uart_alert_test	0.830s	12.904us	1	1	100.00
V2	intr_test	uart_intr_test	0.670s	53.509us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.270s	115.300us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.270s	115.300us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.990s	1.095ms	1	1	100.00
		uart_csr_rw	0.640s	13.485us	1	1	100.00
		uart_csr_aliasing	0.770s	27.026us	1	1	100.00
		uart_same_csr_outstanding	0.750s	84.356us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.990s	1.095ms	1	1	100.00
		uart_csr_rw	0.640s	13.485us	1	1	100.00
		uart_csr_aliasing	0.770s	27.026us	1	1	100.00
		uart_same_csr_outstanding	0.750s	84.356us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.170s	117.542us	1	1	100.00
		uart_tl_intg_err	1.350s	159.583us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.350s	159.583us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	18.870s	2.042ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.92200094134563285169826278705721322882247056588547805206203088413073439056507
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 322170805 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 322170805 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 325010805 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 325010805 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 332290805 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 12,                                 clk_pulses: 0