CHIP Simulation Results

Tuesday September 30 2025 16:05:14 UTC

GitHub Revision: `098ab72`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.053m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.053m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.215m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	37.988s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	21.478s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.272m	6.742ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.272m	6.742ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.272m	6.742ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	31.690s	10.100us	0	1	0.00
		chip_sw_example_manufacturer	2.512m		0	1	0.00
		chip_sw_example_concurrency	4.969m	4.683ms	1	1	100.00
		chip_sw_uart_smoketest_signed	13.823s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.740s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	14.560s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	14.560s		0	1	0.00
V1	xbar_smoke	xbar_smoke	9.240s	12.439us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.587m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	12.756m	8.214ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	5.944m	5.944ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	11.799s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	13.052s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	21.326s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	15.419s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	2.860s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.860s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.347m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.219m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.430m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.430m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.074m	3.256ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.112m	4.878ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.423m	14.351ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	13.079s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	14.439s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	14.077m	18.848ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.084m	5.851ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	24.297m	18.019ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	24.297m	18.019ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	12.561s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.078m	3.850ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.078m	3.850ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	8.304m	18.018ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.431m	5.774ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	6.007m	3.913ms	1	1	100.00
		chip_sw_aes_idle	5.172m	4.954ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.430m	4.421ms	1	1	100.00
		chip_sw_kmac_idle	4.624m	4.315ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	12.771m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	11.540m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	12.006m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	13.930m	12.019ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	13.630s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.792s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.904s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.701s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.822s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.722s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.066s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	13.630s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.792s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.904s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.701s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.822s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.722s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.066s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	13.536s		0	1	0.00
		chip_sw_aes_enc_jitter_en	37.030s	10.320us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	36.360s	10.240us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	40.120s	10.220us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	37.040s	10.140us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.569s		0	1	0.00
		chip_sw_clkmgr_jitter	3.424m	3.219ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.066m	4.070ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	12.116s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	37.820s	10.320us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	37.110s	10.400us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	35.370s	10.400us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	42.570s	10.140us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	35.770s	10.200us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.340s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.848s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.387s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.852s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	21.889m	16.224ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.459m	12.777ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	5.078m	3.850ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	14.175s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.459m	12.777ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	16.279s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	11.713s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	12.972s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	16.664s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	11.610s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	21.889m	16.224ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.423m	14.351ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	27.184m	20.019ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	9.799m	9.909ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	7.727m	6.215ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.770m	4.135ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	21.889m	16.224ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	13.707s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	14.555s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	21.889m	16.224ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	11.808s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	7.727m	6.215ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	13.503s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	12.545s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	13.155s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	12.671s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.909s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	12.139s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	14.555s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	19.393s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	19.911s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	19.393s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	19.393s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	19.393s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.430m	7.346ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	16.594s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	21.091s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	15.580s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	19.895s		0	1	0.00
		chip_sw_lc_ctrl_transition	19.393s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	7.710m	7.946ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	9.431m	10.873ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	16.287s		0	1	0.00
		chip_prim_tl_access	14.490m	19.188ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	13.630s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.792s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.904s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.701s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.822s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.722s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.066s		0	1	0.00
		chip_rv_dm_lc_disabled	14.077m	18.848ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.584m	4.416ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	37.030s	10.320us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.866m	5.117ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.172m	4.954ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.062m	3.947ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	36.360s	10.240us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.430m	4.421ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.176m	3.986ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.717m	5.925ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	37.040s	10.140us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	7.710m	7.946ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	19.393s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	35.910s	10.180us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.431m	6.071ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.624m	4.315ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	15.140s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	15.140s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	14.785s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.399m	3.459ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.942s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	7.710m	7.946ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	40.120s	10.220us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	17.173s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	13.536s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	6.007m	3.913ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	6.007m	3.913ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	6.007m	3.913ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.098m	6.282ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.431m	10.873ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.431m	10.873ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	7.177m	7.445ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.569s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	16.287s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	21.889m	16.224ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.430m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	19.393s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.098m	6.282ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.710m	7.946ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.177m	7.445ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.518m	4.156ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.098m	6.282ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.710m	7.946ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.177m	7.445ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.518m	4.156ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	19.393s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	12.447s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	19.911s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	16.594s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	21.091s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	15.580s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	19.895s		0	1	0.00
		chip_sw_lc_ctrl_transition	19.393s		0	1	0.00
		chip_prim_tl_access	14.490m	19.188ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	14.490m	19.188ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	14.510s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	12.161s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.848s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	13.536s		0	1	0.00
		chip_sw_aes_enc_jitter_en	37.030s	10.320us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	36.360s	10.240us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	40.120s	10.220us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	37.040s	10.140us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.569s		0	1	0.00
		chip_sw_clkmgr_jitter	3.424m	3.219ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.862m	6.436ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.862m	6.436ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.955m	4.778ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.590m	4.612ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.673m	4.216ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	9.429m	6.043ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.714m	5.129ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.677m	5.307ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.518m	4.156ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	27.184m	20.019ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	27.184m	20.019ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.207m	4.157ms	1	1	100.00
		chip_sw_aon_timer_smoketest	4.389m	4.732ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.298m	4.854ms	1	1	100.00
		chip_sw_csrng_smoketest	2.833m	3.206ms	1	1	100.00
		chip_sw_gpio_smoketest	3.551m	3.238ms	1	1	100.00
		chip_sw_hmac_smoketest	4.220m	4.657ms	1	1	100.00
		chip_sw_kmac_smoketest	4.646m	4.957ms	1	1	100.00
		chip_sw_otbn_smoketest	4.413m	4.602ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	2.977m	3.178ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.994m	4.552ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.508m	6.571ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.413m	3.589ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.759m	3.313ms	1	1	100.00
		chip_sw_uart_smoketest	3.388m	3.975ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.799s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	13.823s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.587m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	13.566s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.620m	4.755ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.704m	4.910ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.972m	6.024ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	35.064m	60.000ms	0	1	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	11.765s		0	1	0.00
		chip_rv_dm_lc_disabled	14.077m	18.848ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	14.243s		0	1	0.00
		chip_sw_lc_walkthrough_prod	13.889s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	13.194s		0	1	0.00
		chip_sw_lc_walkthrough_rma	11.734s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	11.765s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	12.517s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	11.711s		0	1	0.00
		rom_volatile_raw_unlock	14.090s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	12.422s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.391m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.769m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.782m	4.957ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.782m	4.957ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	14.560s		0	1	0.00
		chip_same_csr_outstanding	12.210s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	14.560s		0	1	0.00
		chip_same_csr_outstanding	12.210s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	35.100s	34.822us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.790s	12.132us	1	1	100.00
		xbar_smoke_large_delays	4.451m	2.307ms	1	1	100.00
		xbar_smoke_slow_rsp	5.152m	1.909ms	1	1	100.00
		xbar_random_zero_delays	13.000s	14.629us	1	1	100.00
		xbar_random_large_delays	15.031m	7.519ms	1	1	100.00
		xbar_random_slow_rsp	4.019m	1.472ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.117m	137.598us	1	1	100.00
		xbar_error_and_unmapped_addr	1.277m	157.456us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	2.403m	387.247us	1	1	100.00
		xbar_error_and_unmapped_addr	1.277m	157.456us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	34.570s	35.276us	1	1	100.00
		xbar_access_same_device_slow_rsp	30.278m	11.514ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	38.750s	36.584us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.637m	77.668us	1	1	100.00
		xbar_stress_all_with_error	8.310m	1.338ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	14.509m	397.394us	1	1	100.00
		xbar_stress_all_with_reset_error	13.529m	747.694us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	12.117s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.515s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	13.928s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	13.148s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	12.106s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	12.423s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.429s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	12.805s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.900s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	13.104s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	13.127s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.980s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	14.872s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.051m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	57.302s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.042m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	1.012m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.177m		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	1.032m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	55.798s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	48.595s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	41.656s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	56.087s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	1.027m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	53.244s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	51.930s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	33.160s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	27.758s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	14.479s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.960s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.517s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	13.340s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	13.318s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	13.821s		0	1	0.00
		rom_e2e_asm_init_dev	13.080s		0	1	0.00
		rom_e2e_asm_init_prod	12.385s		0	1	0.00
		rom_e2e_asm_init_prod_end	12.235s		0	1	0.00
		rom_e2e_asm_init_rma	12.463s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.934s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.526s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	12.088s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	13.409s		0	1	0.00
V2		TOTAL			64	205	31.22
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.900m	5.614ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.430m	4.081ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	12.380s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.074s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.692s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	12.258s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	21.889m	16.224ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	13.975s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	18.130m	13.881ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	14.843s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	12.703s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	12.380s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.074s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.692s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	12.641s		0	1	0.00
		rom_e2e_jtag_inject_dev	12.061s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.537s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.153s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	22.292m	15.327ms	1	1	100.00
		chip_sw_entropy_src_kat_test	3.824m	4.488ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	4.278m	5.635ms	1	1	100.00
		chip_plic_all_irqs_0	9.943m	5.843ms	1	1	100.00
		chip_plic_all_irqs_10	10.438m	7.343ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.707m	5.510ms	1	1	100.00
		chip_sw_dma_abort	4.745m	4.957ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	12.323s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.696s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.445s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	13.170s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.652s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.993s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.287s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	12.614s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	12.437s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.813s		0	1	0.00
		chip_sw_entropy_src_smoketest	4.546m	5.611ms	1	1	100.00
		chip_sw_mbx_smoketest	3.976m	5.230ms	1	1	100.00
		TOTAL			78	250	31.20

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.45000643172635778494021934466609898068228386441292094427376973781400569751002
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 138.696s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.107668685328287449348056290168404082220123863939750062640485575478553319420447
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 133.561s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.9223744392120394432607370030474680781891209811092330269448146445775400175794
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Target //sw/device/tests:sleep_pin_wake_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 128.766s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.105509261849928507900961676022915928503842517220622735905399889409111191552067
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 121.695s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.102646856953116357827248482577662127565610369379617302244560881833335056059168
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Target //sw/device/tests:uart_tx_rx_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 112.641s, Critical Path: 0.00s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.110439779673398949599887035268189862242399397524375135118104403111018626957986
    Line 380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.45142730659752573727751382255827502434060267792832184214973796794734821710243
    Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.88347539875376542850379353792719834996697234531426176611196613150048526976193
    Line 378, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.90656964267491118007234932385767108844131046704290256858284021130801870637334
    Line 380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.105740906583299190701907067871954201889537747920203090277848365332166014693211
    Line 380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 5 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.73349779570964179426355620002545118860359585493739633722629042261827448842605
Line 420, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20018.535745 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20018.535745 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.96980191274737313710663200436807836338220999008543283242302151333672930475372
Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18018.672531 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.672531 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.85112433464970640794908425749779399105354844737727395976490740510349172932539
Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18018.403913 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.403913 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.105654717717815026001363064026097783845999339212411784108518028298959412960416
Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12018.543463 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.543463 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.2853627498326816402176657219074055494099960341024076071390399752299773961874
Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12026.903114 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.903114 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.2670562830426488296057749772708853182768391369877825560817616337539975275406
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.17700645386053877728889542520363472411101204540752604097704738365092887438884
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.35183922851002452902977282307425430350582394044182328517308938687101351794918
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.95673035818911284731575563749204002359180958565707228112522830184983675791798
Line 415, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 7946.176645 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (2031715489336636434864511351698288763379034341460806877337534534662975599425679584834698208363045369218035098407092163054460537471586564274688207607913564 [0x26cad185aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3a09c61747f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 7946.176645 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.103760619691481343536073754361222734047807191728574323174528400651430064451130
Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 7345.885312 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (1278062064621012750306580204726412062792810639508158882580338866610484861008865112121207555105223118877496791234338847310687571245391360281351370639236188 [0x18670988aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd39e31b9797f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 7345.885312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 2 failures:
- Test chip_sw_clkmgr_off_kmac_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_kmac_trans.12764876205107444716552832379369428557216191385827814901929557853220963943289
    Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log
```
  UVM_ERROR @ 12026.570964 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.570964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_otbn_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_otbn_trans.104748126496664070665301825573071484089310786214834572665144784074528912053099
    Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log
```
  UVM_ERROR @ 12018.581166 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.581166 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.26503153498351367906878536776055820329744528767220472539612759886573518305725
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3255.961941 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: 'h30480000  a_data: 'h5168ee2f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2b  a_opcode: 'h1  a_user: 'h248ad  d_param: 'h0  d_source: 'h2b  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3255.961941 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.74261436416204876630874097916193767365981786892753834521803332920854031317631
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4877.721333 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: 'h30480000  a_data: 'hcd6fe1be  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h9  a_opcode: 'h0  a_user: 'h26930  d_param: 'h0  d_source: 'h9  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4877.721333 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.31016483222786051525542915677787728209816487927679144843277291045724519777526
    Line 1375, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.107695239965849770585168715403815397715612451123099270253415304342917895922797
    Line 435, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5944.006562 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5944.006562 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue has 1 failures:
- Test chip_sw_lc_ctrl_rand_to_scrap has 1 failures.
  - 0.chip_sw_lc_ctrl_rand_to_scrap.28532606354719944271708007256288356030622308034709247387152949399082826564344
    Line 407, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log
```
  UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
  UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.52520611015687730838569525267883507386053182210521935024544084649901507271503
    Line 634, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 6214.760189 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 6214.760189 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.114684462585969551544835394263513148883790600597434361853058304555002514344094
    Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 4777.662164 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4777.662164 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.88785948328461274151979383709122183877069416292568092331277747094576728615764
    Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4611.881965 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4611.881965 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.101063542535273445901114857004354016492599903905426941174875561539081851091921
    Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 3849.856488 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 3849.856488 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.13251322759168527558756077063048092561098969310374961521652480121680838760168
    Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6043.241934 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6043.241934 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.96088100010869966833958366466482373835736548736916496793488727930845653949826
    Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.35026769625086230175825510631235799953984996598919773458916991783912789991693
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 4957.349892 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 4957.349892 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.94688489398667986552241828738986148562889919625750843718093723438460889854134
    Line 376, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14350.950040 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14350.950040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.97384619126997668522740819785416244208092700717704059285979005798627215032205
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.10114970391033748131823969786057911615101267721778326270973040505857241836039
    Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 4956.804908 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4956.804908 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```